cpu_mm_manager3.map.eqn

利用VHDL语言描述的一个简单微处理器,可以通过修改源码来调整指令集,可以在Quartus II上直接运行和编译.

--Mem_DataOut[0] is Mem_DataOut[0]
--operation mode is normal

Mem_DataOut[0]_lut_out = A1L133 & (A1L933 # !AddrR_out[0]) # !A1L133 & A1L733 & AddrR_out[0];
Mem_DataOut[0] = DFFEA(Mem_DataOut[0]_lut_out, clk, VCC, , A1L931, , );


--A1L525 is Select4_process~888
--operation mode is normal

A1L525 = InitialData[0] & (A1L28 # Initial) # !InitialData[0] & A1L28 & !Initial;


--ReadMEM is ReadMEM
--operation mode is normal

ReadMEM_lut_out = A1L665 # A1L765 # ReadMEM & A1L645;
ReadMEM = DFFEA(ReadMEM_lut_out, clk, VCC, , reset, , );


--A1L625 is Select4_process~889
--operation mode is normal

A1L625 = Mem_DataOut[0] & (A1L525 # ReadMEM) # !Mem_DataOut[0] & A1L525 & !ReadMEM;


--Mem_DataOut[1] is Mem_DataOut[1]
--operation mode is normal

Mem_DataOut[1]_lut_out = A1L043 & (A1L843 # !AddrR_out[1]) # !A1L043 & A1L443 & AddrR_out[1];
Mem_DataOut[1] = DFFEA(Mem_DataOut[1]_lut_out, clk, VCC, , A1L931, , );


--A1L725 is Select4_process~890
--operation mode is normal

A1L725 = InitialData[1] & (A1L48 # Initial) # !InitialData[1] & A1L48 & !Initial;


--A1L825 is Select4_process~891
--operation mode is normal

A1L825 = Mem_DataOut[1] & (A1L725 # ReadMEM) # !Mem_DataOut[1] & A1L725 & !ReadMEM;


--Mem_DataOut[2] is Mem_DataOut[2]
--operation mode is normal

Mem_DataOut[2]_lut_out = A1L943 & (A1L753 # !AddrR_out[0]) # !A1L943 & A1L553 & AddrR_out[0];
Mem_DataOut[2] = DFFEA(Mem_DataOut[2]_lut_out, clk, VCC, , A1L931, , );


--A1L925 is Select4_process~892
--operation mode is normal

A1L925 = InitialData[2] & (A1L68 # Initial) # !InitialData[2] & A1L68 & !Initial;


--A1L035 is Select4_process~893
--operation mode is normal

A1L035 = Mem_DataOut[2] & (A1L925 # ReadMEM) # !Mem_DataOut[2] & A1L925 & !ReadMEM;


--Mem_DataOut[3] is Mem_DataOut[3]
--operation mode is normal

Mem_DataOut[3]_lut_out = A1L853 & (A1L663 # !AddrR_out[1]) # !A1L853 & A1L263 & AddrR_out[1];
Mem_DataOut[3] = DFFEA(Mem_DataOut[3]_lut_out, clk, VCC, , A1L931, , );


--A1L135 is Select4_process~894
--operation mode is normal

A1L135 = InitialData[3] & (A1L88 # Initial) # !InitialData[3] & A1L88 & !Initial;


--A1L235 is Select4_process~895
--operation mode is normal

A1L235 = Mem_DataOut[3] & (A1L135 # ReadMEM) # !Mem_DataOut[3] & A1L135 & !ReadMEM;


--Mem_DataOut[4] is Mem_DataOut[4]
--operation mode is normal

Mem_DataOut[4]_lut_out = A1L763 & (A1L573 # !AddrR_out[0]) # !A1L763 & A1L373 & AddrR_out[0];
Mem_DataOut[4] = DFFEA(Mem_DataOut[4]_lut_out, clk, VCC, , A1L931, , );


--A1L335 is Select4_process~896
--operation mode is normal

A1L335 = InitialData[4] & (A1L09 # Initial) # !InitialData[4] & A1L09 & !Initial;


--A1L435 is Select4_process~897
--operation mode is normal

A1L435 = Mem_DataOut[4] & (A1L335 # ReadMEM) # !Mem_DataOut[4] & A1L335 & !ReadMEM;


--Mem_DataOut[5] is Mem_DataOut[5]
--operation mode is normal

Mem_DataOut[5]_lut_out = A1L673 & (A1L483 # !AddrR_out[1]) # !A1L673 & A1L083 & AddrR_out[1];
Mem_DataOut[5] = DFFEA(Mem_DataOut[5]_lut_out, clk, VCC, , A1L931, , );


--A1L535 is Select4_process~898
--operation mode is normal

A1L535 = InitialData[5] & (A1L29 # Initial) # !InitialData[5] & A1L29 & !Initial;


--A1L635 is Select4_process~899
--operation mode is normal

A1L635 = Mem_DataOut[5] & (A1L535 # ReadMEM) # !Mem_DataOut[5] & A1L535 & !ReadMEM;


--Mem_DataOut[6] is Mem_DataOut[6]
--operation mode is normal

Mem_DataOut[6]_lut_out = A1L583 & (A1L393 # !AddrR_out[0]) # !A1L583 & A1L193 & AddrR_out[0];
Mem_DataOut[6] = DFFEA(Mem_DataOut[6]_lut_out, clk, VCC, , A1L931, , );


--A1L735 is Select4_process~900
--operation mode is normal

A1L735 = InitialData[6] & (A1L49 # Initial) # !InitialData[6] & A1L49 & !Initial;


--A1L835 is Select4_process~901
--operation mode is normal

A1L835 = Mem_DataOut[6] & (A1L735 # ReadMEM) # !Mem_DataOut[6] & A1L735 & !ReadMEM;


--Mem_DataOut[7] is Mem_DataOut[7]
--operation mode is normal

Mem_DataOut[7]_lut_out = A1L493 & (A1L204 # !AddrR_out[1]) # !A1L493 & A1L893 & AddrR_out[1];
Mem_DataOut[7] = DFFEA(Mem_DataOut[7]_lut_out, clk, VCC, , A1L931, , );


--A1L935 is Select4_process~902
--operation mode is normal

A1L935 = InitialData[7] & (A1L69 # Initial) # !InitialData[7] & A1L69 & !Initial;


--A1L045 is Select4_process~903
--operation mode is normal

A1L045 = Mem_DataOut[7] & (A1L935 # ReadMEM) # !Mem_DataOut[7] & A1L935 & !ReadMEM;


--R0[0] is R0[0]
--operation mode is normal

R0[0]_lut_out = A1L715 & !A1L304;
R0[0] = DFFEA(R0[0]_lut_out, clk, reset, , A1L224, , );


--R0[1] is R0[1]
--operation mode is normal

R0[1]_lut_out = A1L304 # !A1L815;
R0[1] = DFFEA(R0[1]_lut_out, clk, reset, , A1L224, , );


--R0[2] is R0[2]
--operation mode is normal

R0[2]_lut_out = A1L304 # !A1L915;
R0[2] = DFFEA(R0[2]_lut_out, clk, reset, , A1L224, , );


--R0[3] is R0[3]
--operation mode is normal

R0[3]_lut_out = A1L025 & !A1L304;
R0[3] = DFFEA(R0[3]_lut_out, clk, reset, , A1L224, , );


--R0[4] is R0[4]
--operation mode is normal

R0[4]_lut_out = A1L125;
R0[4] = DFFEA(R0[4]_lut_out, clk, reset, , A1L224, , );


--R0[5] is R0[5]
--operation mode is normal

R0[5]_lut_out = !A1L225;
R0[5] = DFFEA(R0[5]_lut_out, clk, reset, , A1L224, , );


--R0[6] is R0[6]
--operation mode is normal

R0[6]_lut_out = A1L325;
R0[6] = DFFEA(R0[6]_lut_out, clk, reset, , A1L224, , );


--R0[7] is R0[7]
--operation mode is normal

R0[7]_lut_out = !A1L425;
R0[7] = DFFEA(R0[7]_lut_out, clk, reset, , A1L224, , );


--R1[0] is R1[0]
--operation mode is normal

R1[0]_lut_out = A1L715;
R1[0] = DFFEA(R1[0]_lut_out, clk, reset, , A1L144, , );


--R1[1] is R1[1]
--operation mode is normal

R1[1]_lut_out = A1L815;
R1[1] = DFFEA(R1[1]_lut_out, clk, reset, , A1L144, , );


--R1[2] is R1[2]
--operation mode is normal

R1[2]_lut_out = A1L915;
R1[2] = DFFEA(R1[2]_lut_out, clk, reset, , A1L144, , );


--R1[3] is R1[3]
--operation mode is normal

R1[3]_lut_out = A1L025;
R1[3] = DFFEA(R1[3]_lut_out, clk, reset, , A1L144, , );


--R1[4] is R1[4]
--operation mode is normal

R1[4]_lut_out = !A1L125;
R1[4] = DFFEA(R1[4]_lut_out, clk, reset, , A1L144, , );


--R1[5] is R1[5]
--operation mode is normal

R1[5]_lut_out = A1L225;
R1[5] = DFFEA(R1[5]_lut_out, clk, reset, , A1L144, , );


--R1[6] is R1[6]
--operation mode is normal

R1[6]_lut_out = !A1L325;
R1[6] = DFFEA(R1[6]_lut_out, clk, reset, , A1L144, , );


--R1[7] is R1[7]
--operation mode is normal

R1[7]_lut_out = !A1L425;
R1[7] = DFFEA(R1[7]_lut_out, clk, reset, , A1L144, , );


--R2[0] is R2[0]
--operation mode is normal

R2[0]_lut_out = A1L715;
R2[0] = DFFEA(R2[0]_lut_out, clk, reset, , A1L064, , );


--R2[1] is R2[1]
--operation mode is normal

R2[1]_lut_out = A1L815;
R2[1] = DFFEA(R2[1]_lut_out, clk, reset, , A1L064, , );


--R2[2] is R2[2]
--operation mode is normal

R2[2]_lut_out = A1L915;
R2[2] = DFFEA(R2[2]_lut_out, clk, reset, , A1L064, , );


--R2[3] is R2[3]
--operation mode is normal

R2[3]_lut_out = A1L025;
R2[3] = DFFEA(R2[3]_lut_out, clk, reset, , A1L064, , );


--R2[4] is R2[4]
--operation mode is normal

R2[4]_lut_out = A1L125;
R2[4] = DFFEA(R2[4]_lut_out, clk, reset, , A1L064, , );


--R2[5] is R2[5]
--operation mode is normal

R2[5]_lut_out = !A1L225;
R2[5] = DFFEA(R2[5]_lut_out, clk, reset, , A1L064, , );


--R2[6] is R2[6]
--operation mode is normal

R2[6]_lut_out = !A1L325;
R2[6] = DFFEA(R2[6]_lut_out, clk, reset, , A1L064, , );


--R2[7] is R2[7]
--operation mode is normal

R2[7]_lut_out = !A1L425;
R2[7] = DFFEA(R2[7]_lut_out, clk, reset, , A1L064, , );


--MM_RE_A[0] is MM_RE_A[0]
--operation mode is normal

MM_RE_A[0]_lut_out = A1L625;
MM_RE_A[0] = DFFEA(MM_RE_A[0]_lut_out, clk, reset, , A1L942, , );


--AddrR_out[2] is AddrR_out[2]
--operation mode is normal

AddrR_out[2]_lut_out = IP_out[2] & (IR[6] # !A1L421) # !IP_out[2] & IR[6] & A1L421;
AddrR_out[2]_sload_eqn = (Initial & InitialAddr[2]) # (!Initial & AddrR_out[2]_lut_out);
AddrR_out[2] = DFFEA(AddrR_out[2]_sload_eqn, clk, VCC, , A1L31, , );


--MM_RE_9[0] is MM_RE_9[0]
--operation mode is normal

MM_RE_9[0]_lut_out = A1L625;
MM_RE_9[0] = DFFEA(MM_RE_9[0]_lut_out, clk, reset, , A1L932, , );


--AddrR_out[3] is AddrR_out[3]
--operation mode is normal

AddrR_out[3]_lut_out = IP_out[3] & (IR[7] # !A1L421) # !IP_out[3] & IR[7] & A1L421;
AddrR_out[3]_sload_eqn = (Initial & InitialAddr[3]) # (!Initial & AddrR_out[3]_lut_out);
AddrR_out[3] = DFFEA(AddrR_out[3]_sload_eqn, clk, VCC, , A1L31, , );


--MM_RE_8[0] is MM_RE_8[0]
--operation mode is normal

MM_RE_8[0]_lut_out = !A1L625;
MM_RE_8[0] = DFFEA(MM_RE_8[0]_lut_out, clk, reset, , A1L922, , );


--A1L633 is Mux~1191
--operation mode is normal

A1L633 = AddrR_out[3] & (AddrR_out[2] # MM_RE_9[0]) # !AddrR_out[3] & !AddrR_out[2] & !MM_RE_8[0];


--MM_RE_B[0] is MM_RE_B[0]
--operation mode is normal

MM_RE_B[0]_lut_out = A1L625;
MM_RE_B[0] = DFFEA(MM_RE_B[0]_lut_out, clk, reset, , A1L952, , );


--A1L733 is Mux~1192
--operation mode is normal

A1L733 = A1L633 & (MM_RE_B[0] # !AddrR_out[2]) # !A1L633 & MM_RE_A[0] & AddrR_out[2];


--AddrR_out[0] is AddrR_out[0]
--operation mode is normal

AddrR_out[0]_lut_out = IP_out[0] & (IR[4] # !A1L421) # !IP_out[0] & IR[4] & A1L421;
AddrR_out[0]_sload_eqn = (Initial & InitialAddr[0]) # (!Initial & AddrR_out[0]_lut_out);
AddrR_out[0] = DFFEA(AddrR_out[0]_sload_eqn, clk, VCC, , A1L31, , );


--MM_RE_5[0] is MM_RE_5[0]
--operation mode is normal

MM_RE_5[0]_lut_out = !A1L625;
MM_RE_5[0] = DFFEA(MM_RE_5[0]_lut_out, clk, reset, , A1L991, , );


--MM_RE_6[0] is MM_RE_6[0]
--operation mode is normal

MM_RE_6[0]_lut_out = A1L625;
MM_RE_6[0] = DFFEA(MM_RE_6[0]_lut_out, clk, reset, , A1L902, , );


--MM_RE_4[0] is MM_RE_4[0]
--operation mode is normal

MM_RE_4[0]_lut_out = A1L625;
MM_RE_4[0] = DFFEA(MM_RE_4[0]_lut_out, clk, reset, , A1L981, , );


--A1L433 is Mux~1189
--operation mode is normal

A1L433 = AddrR_out[2] & (AddrR_out[3] # MM_RE_6[0]) # !AddrR_out[2] & !AddrR_out[3] & MM_RE_4[0];


--MM_RE_7[0] is MM_RE_7[0]
--operation mode is normal

MM_RE_7[0]_lut_out = A1L625;
MM_RE_7[0] = DFFEA(MM_RE_7[0]_lut_out, clk, reset, , A1L912, , );


--A1L533 is Mux~1190
--operation mode is normal

A1L533 = A1L433 & (MM_RE_7[0] # !AddrR_out[3]) # !A1L433 & !MM_RE_5[0] & AddrR_out[3];


--AddrR_out[1] is AddrR_out[1]
--operation mode is normal

AddrR_out[1]_lut_out = IP_out[1] & (IR[5] # !A1L421) # !IP_out[1] & IR[5] & A1L421;
AddrR_out[1]_sload_eqn = (Initial & InitialAddr[1]) # (!Initial & AddrR_out[1]_lut_out);
AddrR_out[1] = DFFEA(AddrR_out[1]_sload_eqn, clk, VCC, , A1L31, , );


--MM_RE_2[0] is MM_RE_2[0]
--operation mode is normal

MM_RE_2[0]_lut_out = !A1L625;
MM_RE_2[0] = DFFEA(MM_RE_2[0]_lut_out, clk, reset, , A1L961, , );


--MM_RE_1[0] is MM_RE_1[0]
--operation mode is normal

MM_RE_1[0]_lut_out = !A1L625;
MM_RE_1[0] = DFFEA(MM_RE_1[0]_lut_out, clk, reset, , A1L951, , );


--MM_RE_0[0] is MM_RE_0[0]
--operation mode is normal

MM_RE_0[0]_lut_out = !A1L625;
MM_RE_0[0] = DFFEA(MM_RE_0[0]_lut_out, clk, reset, , A1L941, , );


--A1L233 is Mux~1187
--operation mode is normal

A1L233 = AddrR_out[3] & (AddrR_out[2] # !MM_RE_1[0]) # !AddrR_out[3] & !AddrR_out[2] & !MM_RE_0[0];


--MM_RE_3[0] is MM_RE_3[0]
--operation mode is normal

MM_RE_3[0]_lut_out = A1L625;
MM_RE_3[0] = DFFEA(MM_RE_3[0]_lut_out, clk, reset, , A1L971, , );


--A1L333 is Mux~1188
--operation mode is normal

A1L333 = A1L233 & (MM_RE_3[0] # !AddrR_out[2]) # !A1L233 & !MM_RE_2[0] & AddrR_out[2];


--A1L133 is Mux~1185
--operation mode is normal

A1L133 = AddrR_out[1] & (AddrR_out[0] # A1L533) # !AddrR_out[1] & !AddrR_out[0] & A1L333;


--MM_RE_D[0] is MM_RE_D[0]
--operation mode is normal

MM_RE_D[0]_lut_out = A1L625;
MM_RE_D[0] = DFFEA(MM_RE_D[0]_lut_out, clk, reset, , A1L972, , );


--MM_RE_E[0] is MM_RE_E[0]
--operation mode is normal

MM_RE_E[0]_lut_out = A1L625;
MM_RE_E[0] = DFFEA(MM_RE_E[0]_lut_out, clk, reset, , A1L982, , );


--MM_RE_C[0] is MM_RE_C[0]
--operation mode is normal

MM_RE_C[0]_lut_out = A1L625;
MM_RE_C[0] = DFFEA(MM_RE_C[0]_lut_out, clk, reset, , A1L962, , );


--A1L833 is Mux~1193
--operation mode is normal

A1L833 = AddrR_out[2] & (AddrR_out[3] # MM_RE_E[0]) # !AddrR_out[2] & !AddrR_out[3] & MM_RE_C[0];


--MM_RE_F[0] is MM_RE_F[0]
--operation mode is normal

MM_RE_F[0]_lut_out = A1L625;
MM_RE_F[0] = DFFEA(MM_RE_F[0]_lut_out, clk, reset, , A1L992, , );


--A1L933 is Mux~1194
--operation mode is normal

A1L933 = A1L833 & (MM_RE_F[0] # !AddrR_out[3]) # !A1L833 & MM_RE_D[0] & AddrR_out[3];


--WriteMEM is WriteMEM
--operation mode is normal

WriteMEM_lut_out = WriteMEM & (A1L645 # A1L514 & !A1L66) # !WriteMEM & A1L514 & !A1L66;
WriteMEM = DFFEA(WriteMEM_lut_out, clk, VCC, , reset, , );


--A1L931 is Mem_DataOut[0]~28
--operation mode is normal

A1L931 = ReadMEM & reset & !Initial & !WriteMEM;


--R_out[0] is R_out[0]
--operation mode is normal

R_out[0]_lut_out = A1L323 & (R_to_ALU[0] # R_out[0]) # !A1L323 & R2[0] & !R_to_ALU[0];
R_out[0] = DFFEA(R_out[0]_lut_out, clk, VCC, , reset, , );


--DataOut_to_bus is DataOut_to_bus
--operation mode is normal

DataOut_to_bus_lut_out = A1L475 # A1L145 # DataOut_to_bus & A1L745;
DataOut_to_bus = DFFEA(DataOut_to_bus_lut_out, clk, VCC, , reset, , );


--A1L28 is DataOut[0]~216
--operation mode is normal

A1L28 = LCELL(R_out[0] & (A1L28 # DataOut_to_bus) # !R_out[0] & A1L28 & !DataOut_to_bus);


--IR[3] is IR[3]
--operation mode is normal

IR[3]_lut_out = A1L235;
IR[3] = DFFEA(IR[3]_lut_out, clk, reset, , IR_in, , );


--IR[2] is IR[2]
--operation mode is normal

IR[2]_lut_out = A1L035;
IR[2] = DFFEA(IR[2]_lut_out, clk, reset, , IR_in, , );


--IR[1] is IR[1]
--operation mode is normal

IR[1]_lut_out = A1L825;
IR[1] = DFFEA(IR[1]_lut_out, clk, reset, , IR_in, , );


--IR[0] is IR[0]
--operation mode is normal

IR[0]_lut_out = A1L625;
IR[0] = DFFEA(IR[0]_lut_out, clk, reset, , IR_in, , );