segled.syr

使用xilinx公司的FPGA实现了七段码的定时器时钟程序

Release 7.1i - xst H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: segled.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "segled.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "segled"
Output Format                      : NGC
Target Device                      : xc3s200-4-pq208

---- Source Options
Top Module Name                    : segled
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : segled.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "segled.v"
Module <segled> compiled
No errors in compilation
Analysis of file <"segled.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <segled>.
WARNING:Xst:905 - "segled.v" line 83: The signals <secseg1, secseg2, minseg1, minseg2> are missing in the sensitivity list of always block.
Module <segled> is correct for synthesis.
 
    Set property "resynthesize = true" for unit <segled>.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <segled>.
    Related source file is "segled.v".
WARNING:Xst:1780 - Signal <scanclk> is never used or assigned.
    Found 16x8-bit ROM for signal <secseg1>.
    Found 16x3-bit ROM for signal <$n0015>.
    Found 1-of-4 decoder for signal <a>.
    Found 8-bit 4-to-1 multiplexer for signal <seg>.
    Found 28-bit comparator greatequal for signal <$n0000> created at line 45.
    Found 4-bit comparator greatequal for signal <$n0002> created at line 56.
    Found 4-bit comparator greatequal for signal <$n0030> created at line 59.
    Found 4-bit comparator greatequal for signal <$n0031> created at line 62.
    Found 4-bit comparator less for signal <$n0032> created at line 59.
    Found 4-bit comparator less for signal <$n0033> created at line 56.
    Found 4-bit comparator greatequal for signal <$n0034> created at line 65.
    Found 4-bit comparator less for signal <$n0035> created at line 62.
    Found 1-bit register for signal <divclk>.
    Found 28-bit up counter for signal <divcounter>.
    Found 4-bit up counter for signal <mincounter1>.
    Found 4-bit up counter for signal <mincounter2>.
    Found 1-bit register for signal <minseg1<0>>.
    Found 9-bit up counter for signal <scan>.
    Found 4-bit up counter for signal <seccounter1>.
    Found 4-bit up counter for signal <seccounter2>.
    Summary:
	inferred   2 ROM(s).
	inferred   6 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   8 Comparator(s).
	inferred   8 Multiplexer(s).
	inferred   1 Decoder(s).
Unit <segled> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 2
 16x3-bit ROM                      : 1
 16x8-bit ROM                      : 1
# Counters                         : 6
 28-bit up counter                 : 1
 4-bit up counter                  : 4
 9-bit up counter                  : 1
# Registers                        : 2
 1-bit register                    : 2
# Comparators                      : 8
 28-bit comparator greatequal      : 1
 4-bit comparator greatequal       : 4
 4-bit comparator less             : 3
# Multiplexers                     : 1
 8-bit 4-to-1 multiplexer          : 1
# Decoders                         : 1
 1-of-4 decoder                    : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1988 - Unit <segled>: instances <Mcompar__n0030>, <Mcompar__n0032> of unit <LPM_COMPARE_3> and unit <LPM_COMPARE_4> are dual, second instance is removed
WARNING:Xst:1988 - Unit <segled>: instances <Mcompar__n0031>, <Mcompar__n0035> of unit <LPM_COMPARE_2> and unit <LPM_COMPARE_5> are dual, second instance is removed
WARNING:Xst:1988 - Unit <segled>: instances <Mcompar__n0033>, <Mcompar__n0002> of unit <LPM_COMPARE_5> and unit <LPM_COMPARE_2> are dual, second instance is removed

Optimizing unit <segled> ...
Loading device for application Rf_Device from file '3s200.nph' in environment D:/Xilinx ISE 7.1i.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block segled, actual ratio is 3.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : segled.ngr
Top Level Output File Name         : segled
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics