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来自「使用xilinx公司的FPGA实现了七段码的定时器时钟程序」· SYR 代码 · 共 409 行 · 第 1/2 页

# IOs                              : 13

Macro Statistics :
# ROMs                             : 2
#      16x3-bit ROM                : 1
#      16x8-bit ROM                : 1
# Registers                        : 8
#      1-bit register              : 2
#      28-bit register             : 6
# Multiplexers                     : 1
#      8-bit 4-to-1 multiplexer    : 1
# Decoders                         : 1
#      1-of-4 decoder              : 1
# Adders/Subtractors               : 6
#      28-bit adder                : 6
# Comparators                      : 8
#      28-bit comparator greatequal: 1
#      4-bit comparator greatequal : 4
#      4-bit comparator less       : 3

Cell Usage :
# BELS                             : 212
#      GND                         : 1
#      INV                         : 11
#      LUT1                        : 19
#      LUT1_L                      : 19
#      LUT2                        : 10
#      LUT2_L                      : 1
#      LUT3                        : 24
#      LUT3_L                      : 1
#      LUT4                        : 28
#      LUT4_D                      : 2
#      LUT4_L                      : 4
#      MUXCY                       : 48
#      MUXF5                       : 8
#      VCC                         : 1
#      XORCY                       : 35
# FlipFlops/Latches                : 55
#      FD                          : 9
#      FDE                         : 1
#      FDR                         : 33
#      FDRE                        : 12
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 12
#      OBUF                        : 12
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200pq208-4 

 Number of Slices:                      65  out of   1920     3%  
 Number of Slice Flip Flops:            55  out of   3840     1%  
 Number of 4 input LUTs:               108  out of   3840     2%  
 Number of bonded IOBs:                 13  out of    141     9%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 38    |
divclk:Q                           | NONE                   | 17    |
-----------------------------------+------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 6.911ns (Maximum Frequency: 144.697MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 11.132ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 6.834ns (frequency: 146.329MHz)
  Total number of paths / destination ports: 1264 / 67
-------------------------------------------------------------------------
Delay:               6.834ns (Levels of Logic = 14)
  Source:            divcounter_0 (FF)
  Destination:       divcounter_26 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: divcounter_0 to divcounter_26
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              2   0.720   1.216  divcounter_0 (divcounter_0)
     LUT4_L:I0->LO         1   0.551   0.000  Andlut (N4)
     MUXCY:S->O            1   0.500   0.000  Andcy (And_cyo)
     MUXCY:CI->O           1   0.064   0.000  Andcy_rn_0 (And_cyo1)
     MUXCY:CI->O           1   0.064   0.000  norcy (nor_cyo)
     MUXCY:CI->O           1   0.064   0.000  norcy_rn_0 (nor_cyo1)
     MUXCY:CI->O           1   0.064   0.000  Andcy_rn_1 (And_cyo2)
     MUXCY:CI->O           1   0.064   0.000  norcy_rn_1 (nor_cyo2)
     MUXCY:CI->O           1   0.064   0.000  Andcy_rn_2 (And_cyo3)
     MUXCY:CI->O           1   0.064   0.000  norcy_rn_2 (nor_cyo3)
     MUXCY:CI->O           1   0.064   0.000  Andcy_rn_3 (And_cyo4)
     MUXCY:CI->O           1   0.064   0.000  Andcy_rn_4 (And_cyo5)
     MUXCY:CI->O           1   0.064   0.000  norcy_rn_3 (nor_cyo4)
     MUXCY:CI->O           1   0.064   0.000  Andcy_rn_5 (And_cyo6)
     MUXCY:CI->O          29   0.281   1.836  norcy_rn_4 (_n0000)
     FDR:R                     1.026          divcounter_0
    ----------------------------------------
    Total                      6.834ns (3.782ns logic, 3.052ns route)
                                       (55.3% logic, 44.7% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'divclk:Q'
  Clock period: 6.911ns (frequency: 144.697MHz)
  Total number of paths / destination ports: 297 / 45
-------------------------------------------------------------------------
Delay:               6.911ns (Levels of Logic = 3)
  Source:            mincounter1_2 (FF)
  Destination:       mincounter2_3 (FF)
  Source Clock:      divclk:Q rising
  Destination Clock: divclk:Q rising

  Data Path: mincounter1_2 to mincounter2_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q            10   0.720   1.473  mincounter1_2 (mincounter1_2)
     LUT3:I0->O            1   0.551   0.996  Ker4_SW0_SW0 (N121)
     LUT4_D:I1->LO         1   0.551   0.126  Ker4 (N141)
     LUT4:I3->O            4   0.551   0.917  _n0006 (_n0006)
     FDRE:R                    1.026          mincounter2_0
    ----------------------------------------
    Total                      6.911ns (3.399ns logic, 3.512ns route)
                                       (49.2% logic, 50.8% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 31 / 12
-------------------------------------------------------------------------
Offset:              9.960ns (Levels of Logic = 3)
  Source:            scan_7 (FF)
  Destination:       seg<7> (PAD)
  Source Clock:      clk rising

  Data Path: scan_7 to seg<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q              20   0.720   1.884  scan_7 (scan_7)
     LUT3:I0->O            1   0.551   0.000  scan<7>14 (MUX_BLOCK_N16)
     MUXF5:I1->O           1   0.360   0.801  Mmux_seg_seg<0>_seg<0>_rn_5 (seg_7_OBUF)
     OBUF:I->O                 5.644          seg_7_OBUF (seg<7>)
    ----------------------------------------
    Total                      9.960ns (7.275ns logic, 2.685ns route)
                                       (73.0% logic, 27.0% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'divclk:Q'
  Total number of paths / destination ports: 109 / 8
-------------------------------------------------------------------------
Offset:              11.132ns (Levels of Logic = 4)
  Source:            seccounter1_0 (FF)
  Destination:       seg<4> (PAD)
  Source Clock:      divclk:Q rising

  Data Path: seccounter1_0 to seg<4>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q             13   0.720   1.509  seccounter1_0 (seccounter1_0)
     LUT4:I0->O            1   0.551   0.996  Mrom_secseg1_inst_lut4_41 (secseg1<4>)
     LUT3:I1->O            1   0.551   0.000  scan<7>9 (MUX_BLOCK_N11)
     MUXF5:I0->O           1   0.360   0.801  Mmux_seg_seg<0>_seg<0>_rn_2 (seg_4_OBUF)
     OBUF:I->O                 5.644          seg_4_OBUF (seg<4>)
    ----------------------------------------
    Total                     11.132ns (7.826ns logic, 3.306ns route)
                                       (70.3% logic, 29.7% route)

=========================================================================
CPU : 9.20 / 10.14 s | Elapsed : 10.00 / 10.00 s
 
--> 

Total memory usage is 99852 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    5 (   0 filtered)
Number of infos    :    1 (   0 filtered)