wsm320.rpt

在MAXPULS II环境下

-- synthesized logic cell 
_LC6_A15 = LCELL( _EQ069);
  _EQ069 =  _LC5_A14
         #  _LC7_A14 & !_LC7_A17
         #  _LC6_A14 &  _LC7_A17;

-- Node name is '~610~2' 
-- Equation name is '~610~2', location is LC3_A15, type is buried.
-- synthesized logic cell 
_LC3_A15 = LCELL( _EQ070);
  _EQ070 =  _LC6_A15
         #  _LC5_A21
         #  _LC1_A14 & !_LC8_A21;

-- Node name is ':610' 
-- Equation name is '_LC7_A13', type is buried 
_LC7_A13 = LCELL( _EQ071);
  _EQ071 = !_LC2_A12 &  _LC2_A13 &  _LC3_A13
         #  _LC3_A15;

-- Node name is '~611~1' 
-- Equation name is '~611~1', location is LC7_A15, type is buried.
-- synthesized logic cell 
_LC7_A15 = LCELL( _EQ072);
  _EQ072 = !_LC1_A24 & !_LC7_A17
         # !_LC5_A17;

-- Node name is '~611~2' 
-- Equation name is '~611~2', location is LC8_A15, type is buried.
-- synthesized logic cell 
_LC8_A15 = LCELL( _EQ073);
  _EQ073 =  _LC4_A15 & !_LC4_A21
         #  _LC7_A15
         #  _LC5_A21;

-- Node name is ':611' 
-- Equation name is '_LC5_A1', type is buried 
_LC5_A1  = LCELL( _EQ074);
  _EQ074 =  _LC3_A1
         #  _LC8_A15
         #  _LC4_A14 & !_LC6_A17;

-- Node name is ':637' 
-- Equation name is '_LC8_A13', type is buried 
_LC8_A13 = LCELL( _EQ075);
  _EQ075 =  _LC8_A13
         #  _LC2_A15 & !_LC2_A19 &  _LC7_A24;

-- Node name is '~658~1' 
-- Equation name is '~658~1', location is LC7_A24, type is buried.
-- synthesized logic cell 
!_LC7_A24 = _LC7_A24~NOT;
_LC7_A24~NOT = LCELL( _EQ076);
  _EQ076 = !_LC1_A24
         # !_LC8_A19
         #  _LC4_A14;

-- Node name is ':659' 
-- Equation name is '_LC8_A22', type is buried 
_LC8_A22 = LCELL( _EQ077);
  _EQ077 = !_LC2_A19 &  _LC7_A24 &  _LC8_A22
         # !_LC2_A15;

-- Node name is '~680~1' 
-- Equation name is '~680~1', location is LC4_A24, type is buried.
-- synthesized logic cell 
_LC4_A24 = LCELL( _EQ078);
  _EQ078 =  _LC2_A15 & !_LC2_A19;

-- Node name is ':681' 
-- Equation name is '_LC5_A24', type is buried 
_LC5_A24 = LCELL( _EQ079);
  _EQ079 =  _LC4_A24 &  _LC5_A24 & !_LC6_A24
         # !_LC1_A24;

-- Node name is '~702~1' 
-- Equation name is '~702~1', location is LC2_A15, type is buried.
-- synthesized logic cell 
!_LC2_A15 = _LC2_A15~NOT;
_LC2_A15~NOT = LCELL( _EQ080);
  _EQ080 =  _LC4_A15
         #  _LC8_A14
         #  _LC1_A14;

-- Node name is '~702~2' 
-- Equation name is '~702~2', location is LC3_A24, type is buried.
-- synthesized logic cell 
_LC3_A24 = LCELL( _EQ081);
  _EQ081 =  _LC1_A24 &  _LC2_A15 & !_LC2_A19 & !_LC4_A14;

-- Node name is ':703' 
-- Equation name is '_LC2_A24', type is buried 
_LC2_A24 = LCELL( _EQ082);
  _EQ082 =  _LC2_A24 &  _LC3_A24
         # !_LC8_A19;

-- Node name is ':729' 
-- Equation name is '_LC5_A13', type is buried 
_LC5_A13 = LCELL( _EQ083);
  _EQ083 = !_LC2_A15
         # !_LC7_A24
         #  _LC2_A13 &  _LC5_A13;

-- Node name is ':850' 
-- Equation name is '_LC8_A1', type is buried 
_LC8_A1  = LCELL( _EQ084);
  _EQ084 = !_LC1_A12 & !_LC5_A12 &  _LC8_B5
         #  _LC4_A12 & !_LC5_A12;

-- Node name is ':853' 
-- Equation name is '_LC5_B5', type is buried 
_LC5_B5  = LCELL( _EQ085);
  _EQ085 =  _LC1_B5 &  _LC2_B9
         # !_LC4_A1;

-- Node name is '~856~1' 
-- Equation name is '~856~1', location is LC2_B9, type is buried.
-- synthesized logic cell 
_LC2_B9  = LCELL( _EQ086);
  _EQ086 = !_LC1_A12 & !_LC4_A12;

-- Node name is ':860' 
-- Equation name is '_LC6_B5', type is buried 
_LC6_B5  = LCELL( _EQ087);
  _EQ087 =  _LC2_B9 &  _LC3_B5 &  _LC4_A1
         #  _LC2_A12;

-- Node name is ':866' 
-- Equation name is '_LC1_A1', type is buried 
_LC1_A1  = LCELL( _EQ088);
  _EQ088 = !_LC2_A12 & !_LC5_A13 &  _LC8_A1
         # !_LC2_A12 &  _LC3_A12 & !_LC5_A13;

-- Node name is '~930~1' 
-- Equation name is '~930~1', location is LC6_A1, type is buried.
-- synthesized logic cell 
!_LC6_A1 = _LC6_A1~NOT;
_LC6_A1~NOT = LCELL( _EQ089);
  _EQ089 = !_LC2_A12 &  _LC4_A1;

-- Node name is ':933' 
-- Equation name is '_LC3_B8', type is buried 
_LC3_B8  = LCELL( _EQ090);
  _EQ090 =  _LC1_B8 & !_LC4_A12
         #  _LC1_A12 & !_LC4_A12
         #  _LC6_A1;

-- Node name is ':934' 
-- Equation name is '_LC7_B9', type is buried 
_LC7_B9  = LCELL( _EQ091);
  _EQ091 =  _LC2_B9 & !_LC5_A13 &  _LC6_B9
         # !_LC5_A13 &  _LC6_A1;

-- Node name is '~935~1' 
-- Equation name is '~935~1', location is LC7_B8, type is buried.
-- synthesized logic cell 
_LC7_B8  = LCELL( _EQ092);
  _EQ092 = !_LC5_A13 & !_LC6_A1;

-- Node name is ':935' 
-- Equation name is '_LC5_B9', type is buried 
_LC5_B9  = LCELL( _EQ093);
  _EQ093 = !_LC1_A12 &  _LC4_B9 &  _LC7_B8
         #  _LC4_A12 &  _LC7_B8;

-- Node name is '~936~1' 
-- Equation name is '~936~1', location is LC4_A1, type is buried.
-- synthesized logic cell 
!_LC4_A1 = _LC4_A1~NOT;
_LC4_A1~NOT = LCELL( _EQ094);
  _EQ094 =  _LC3_A12
         #  _LC5_A12;

-- Node name is ':957' 
-- Equation name is '_LC1_B9', type is buried 
!_LC1_B9 = _LC1_B9~NOT;
_LC1_B9~NOT = LCELL( _EQ095);
  _EQ095 =  _LC6_B9
         #  _LC4_B9
         #  _LC2_B8
         #  _LC1_B8;

-- Node name is ':986' 
-- Equation name is '_LC4_B8', type is buried 
_LC4_B8  = LCELL( _EQ096);
  _EQ096 =  _LC1_B8 & !_LC1_B9 &  _LC2_B8 &  _LC5_A13
         # !_LC1_B8 & !_LC1_B9 & !_LC2_B8 &  _LC5_A13;

-- Node name is ':992' 
-- Equation name is '_LC6_B9', type is buried 
_LC6_B9  = DFFE( _EQ097,  hz1,  VCC,  VCC,  VCC);
  _EQ097 =  _LC7_B9
         #  _LC6_B8 & !_LC8_B9
         #  _LC1_B9 &  _LC6_B8;

-- Node name is ':993' 
-- Equation name is '_LC4_B9', type is buried 
_LC4_B9  = DFFE( _EQ098,  hz1,  VCC,  VCC,  VCC);
  _EQ098 = !_LC1_B9 & !_LC3_B9 &  _LC5_A13
         #  _LC5_B9;

-- Node name is ':994' 
-- Equation name is '_LC2_B8', type is buried 
_LC2_B8  = DFFE( _EQ099,  hz1,  VCC,  VCC,  VCC);
  _EQ099 =  _LC4_B8
         #  _LC2_B8 &  _LC7_B8
         # !_LC2_B9 &  _LC7_B8;

-- Node name is ':995' 
-- Equation name is '_LC1_B8', type is buried 
_LC1_B8  = DFFE( _EQ100,  hz1,  VCC,  VCC,  VCC);
  _EQ100 = !_LC1_B8 &  _LC6_B8
         #  _LC3_B8 & !_LC5_A13;

-- Node name is ':1010' 
-- Equation name is '_LC7_B5', type is buried 
_LC7_B5  = LCELL( _EQ101);
  _EQ101 =  _LC1_B5 &  _LC3_B5
         #  _LC3_B5 &  _LC8_B5
         # !_LC1_B5 &  _LC1_B9 & !_LC3_B5 & !_LC8_B5
         # !_LC1_B9 &  _LC3_B5;

-- Node name is '~1021~1' 
-- Equation name is '~1021~1', location is LC6_B8, type is buried.
-- synthesized logic cell 
_LC6_B8  = LCELL( _EQ102);
  _EQ102 = !_LC1_B9 &  _LC5_A13
         #  _LC5_A13 &  _LC5_B8
         #  _LC2_B5 &  _LC5_A13;

-- Node name is ':1021' 
-- Equation name is '_LC8_B8', type is buried 
_LC8_B8  = LCELL( _EQ103);
  _EQ103 =  _LC2_B5 &  _LC5_A13 &  _LC5_B8
         # !_LC1_B9 &  _LC5_A13 &  _LC5_B8;

-- Node name is ':1023' 
-- Equation name is '_LC4_B5', type is buried 
_LC4_B5  = LCELL( _EQ104);
  _EQ104 =  _LC1_B5 &  _LC6_B8 &  _LC8_B5
         # !_LC1_B5 &  _LC1_B9 &  _LC6_B8 & !_LC8_B5
         #  _LC1_B5 & !_LC1_B9 &  _LC6_B8;

-- Node name is ':1029' 
-- Equation name is '_LC5_B8', type is buried 
_LC5_B8  = DFFE( _EQ105,  hz1,  VCC,  VCC,  VCC);
  _EQ105 =  _LC8_B8
         #  _LC2_B9 &  _LC5_B8 &  _LC7_B8;

-- Node name is ':1030' 
-- Equation name is '_LC3_B5', type is buried 
_LC3_B5  = DFFE( _EQ106,  hz1,  VCC,  VCC,  VCC);
  _EQ106 = !_LC5_A13 &  _LC6_B5
         #  _LC6_B8 &  _LC7_B5;

-- Node name is ':1031' 
-- Equation name is '_LC1_B5', type is buried 
_LC1_B5  = DFFE( _EQ107,  hz1,  VCC,  VCC,  VCC);
  _EQ107 =  _LC4_B5
         # !_LC2_A12 & !_LC5_A13 &  _LC5_B5;

-- Node name is ':1032' 
-- Equation name is '_LC8_B5', type is buried 
_LC8_B5  = DFFE( _EQ108,  hz1,  VCC,  VCC,  VCC);
  _EQ108 =  _LC1_A1
         # !_LC1_B9 &  _LC6_B8 &  _LC8_B5
         #  _LC1_B9 &  _LC6_B8 & !_LC8_B5;



Project Information                          f:\作业\ic\washmachine\wsm320.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:04


Memory Allocated
-----------------

Peak memory allocated during compilation  = 13,885K