📄 wsm318.rpt
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Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\washmachine\wsm318.rpt
wsm318
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
39 19 B FF + t 0 0 0 4 1 1 0 l1
41 17 B FF + t 0 0 0 1 4 1 0 l2
36 22 B FF + t 0 0 0 1 1 0 0 l3
40 18 B FF + t 0 0 0 3 3 1 0 sound
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\washmachine\wsm318.rpt
wsm318
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(37) 21 B DFFE + t 0 0 0 1 2 1 1 px (:227)
(38) 20 B TFFE + t 0 0 0 1 0 2 0 st (:246)
(34) 23 B TFFE + t 0 0 0 1 0 3 1 W (:365)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\washmachine\wsm318.rpt
wsm318
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------- LC19 l1
| +----------- LC17 l2
| | +--------- LC22 l3
| | | +------- LC18 sound
| | | | +----- LC21 px
| | | | | +--- LC20 st
| | | | | | +- LC23 W
| | | | | | |
| | | | | | | Other LABs fed by signals
| | | | | | | that feed LAB 'B'
LC | | | | | | | | A B | Logic cells that feed LAB 'B':
LC19 -> * - - - - - - | - * | <-- l1
LC17 -> - * - - - - - | - * | <-- l2
LC18 -> - - - * - - - | - * | <-- sound
LC21 -> - * - - * - - | - * | <-- px
LC20 -> - * - * - * - | - * | <-- st
LC23 -> - * * * * - * | - * | <-- W
Pin
43 -> - - - - - - - | - - | <-- hz1
9 -> - - - * - - - | - * | <-- hz1k
8 -> * - - - - - - | - * | <-- key1
7 -> * - - - - - - | - * | <-- key2
6 -> * - - - - - - | - * | <-- key3
5 -> - - - * - - - | - * | <-- s
4 -> * * * * * * * | - * | <-- start
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\washmachine\wsm318.rpt
wsm318
** EQUATIONS **
hz1 : INPUT;
hz1k : INPUT;
key1 : INPUT;
key2 : INPUT;
key3 : INPUT;
s : INPUT;
start : INPUT;
-- Node name is 'l1' = ':440'
-- Equation name is 'l1', type is output
l1 = DFFE( _EQ001 $ VCC, GLOBAL( hz1), VCC, VCC, start);
_EQ001 = !key1 & !key2 & !key3 & !l1;
-- Node name is 'l2' = ':450'
-- Equation name is 'l2', type is output
l2 = DFFE( _EQ002 $ GND, GLOBAL( hz1), VCC, VCC, start);
_EQ002 = !px & st & !W
# l2 & W;
-- Node name is 'l3' = ':467'
-- Equation name is 'l3', type is output
l3 = DFFE( W $ GND, GLOBAL( hz1), VCC, VCC, start);
-- Node name is ':227' = 'px'
-- Equation name is 'px', location is LC021, type is buried.
px = DFFE( _EQ003 $ GND, GLOBAL( hz1), VCC, VCC, start);
_EQ003 = px & W;
-- Node name is 'sound' = ':416'
-- Equation name is 'sound', type is output
sound = DFFE( _EQ004 $ GND, GLOBAL( hz1), VCC, VCC, start);
_EQ004 = hz1k & s & !st & !W
# !s & sound & !W
# sound & W;
-- Node name is ':246' = 'st'
-- Equation name is 'st', location is LC020, type is buried.
st = TFFE( GND, GLOBAL( hz1), VCC, VCC, start);
-- Node name is ':365' = 'W'
-- Equation name is 'W', location is LC023, type is buried.
W = TFFE( GND, GLOBAL( hz1), VCC, VCC, start);
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\washmachine\wsm318.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:01
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 10,710K
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