wsm321.rpt

在MAXPULS II环境下

-- Node name is '~610~1' 
-- Equation name is '~610~1', location is LC7_C24, type is buried.
-- synthesized logic cell 
_LC7_C24 = LCELL( _EQ069);
  _EQ069 =  _LC6_C19
         # !_LC4_C16 &  _LC7_C19
         #  _LC4_C16 &  _LC8_C19;

-- Node name is '~610~2' 
-- Equation name is '~610~2', location is LC1_C24, type is buried.
-- synthesized logic cell 
_LC1_C24 = LCELL( _EQ070);
  _EQ070 =  _LC7_C24
         #  _LC6_C21
         #  _LC3_C19 & !_LC8_C21;

-- Node name is ':610' 
-- Equation name is '_LC5_C14', type is buried 
_LC5_C14 = LCELL( _EQ071);
  _EQ071 =  _LC1_C14 & !_LC3_C3 &  _LC7_C14
         #  _LC1_C24;

-- Node name is '~611~1' 
-- Equation name is '~611~1', location is LC2_C23, type is buried.
-- synthesized logic cell 
_LC2_C23 = LCELL( _EQ072);
  _EQ072 = !_LC3_C15 & !_LC4_C16
         # !_LC8_C16;

-- Node name is '~611~2' 
-- Equation name is '~611~2', location is LC8_C24, type is buried.
-- synthesized logic cell 
_LC8_C24 = LCELL( _EQ073);
  _EQ073 =  _LC3_C24 & !_LC4_C24
         #  _LC2_C23
         #  _LC6_C21;

-- Node name is ':611' 
-- Equation name is '_LC4_C1', type is buried 
_LC4_C1  = LCELL( _EQ074);
  _EQ074 =  _LC2_C1
         #  _LC8_C24
         #  _LC1_C19 & !_LC2_C16;

-- Node name is ':637' 
-- Equation name is '_LC8_C14', type is buried 
_LC8_C14 = LCELL( _EQ075);
  _EQ075 =  _LC8_C14
         # !_LC1_C17 &  _LC2_C24 &  _LC8_C23;

-- Node name is '~658~1' 
-- Equation name is '~658~1', location is LC8_C23, type is buried.
-- synthesized logic cell 
!_LC8_C23 = _LC8_C23~NOT;
_LC8_C23~NOT = LCELL( _EQ076);
  _EQ076 = !_LC3_C15
         # !_LC5_C17
         #  _LC1_C19;

-- Node name is ':659' 
-- Equation name is '_LC1_C22', type is buried 
_LC1_C22 = LCELL( _EQ077);
  _EQ077 = !_LC1_C17 &  _LC1_C22 &  _LC8_C23
         # !_LC2_C24;

-- Node name is '~680~1' 
-- Equation name is '~680~1', location is LC5_C23, type is buried.
-- synthesized logic cell 
_LC5_C23 = LCELL( _EQ078);
  _EQ078 = !_LC1_C17 &  _LC2_C24;

-- Node name is ':681' 
-- Equation name is '_LC7_C23', type is buried 
_LC7_C23 = LCELL( _EQ079);
  _EQ079 =  _LC5_C23 & !_LC6_C23 &  _LC7_C23
         # !_LC3_C15;

-- Node name is '~702~1' 
-- Equation name is '~702~1', location is LC2_C24, type is buried.
-- synthesized logic cell 
!_LC2_C24 = _LC2_C24~NOT;
_LC2_C24~NOT = LCELL( _EQ080);
  _EQ080 =  _LC3_C24
         #  _LC4_C19
         #  _LC3_C19;

-- Node name is '~702~2' 
-- Equation name is '~702~2', location is LC1_C23, type is buried.
-- synthesized logic cell 
_LC1_C23 = LCELL( _EQ081);
  _EQ081 = !_LC1_C17 & !_LC1_C19 &  _LC2_C24 &  _LC3_C15;

-- Node name is ':703' 
-- Equation name is '_LC3_C23', type is buried 
_LC3_C23 = LCELL( _EQ082);
  _EQ082 =  _LC1_C23 &  _LC3_C23
         # !_LC5_C17;

-- Node name is ':729' 
-- Equation name is '_LC3_C14', type is buried 
_LC3_C14 = LCELL( _EQ083);
  _EQ083 = !_LC2_C24
         # !_LC8_C23
         #  _LC3_C14 &  _LC7_C14;

-- Node name is ':850' 
-- Equation name is '_LC7_C1', type is buried 
_LC7_C1  = LCELL( _EQ084);
  _EQ084 = !_LC1_C3 &  _LC5_C1 & !_LC5_C3
         # !_LC1_C3 &  _LC2_C3;

-- Node name is ':853' 
-- Equation name is '_LC6_C4', type is buried 
_LC6_C4  = LCELL( _EQ085);
  _EQ085 =  _LC1_C4 &  _LC2_C8
         # !_LC6_C1;

-- Node name is '~856~1' 
-- Equation name is '~856~1', location is LC2_C8, type is buried.
-- synthesized logic cell 
_LC2_C8  = LCELL( _EQ086);
  _EQ086 = !_LC2_C3 & !_LC5_C3;

-- Node name is ':860' 
-- Equation name is '_LC7_C4', type is buried 
_LC7_C4  = LCELL( _EQ087);
  _EQ087 =  _LC2_C8 &  _LC5_C4 &  _LC6_C1
         #  _LC3_C3;

-- Node name is ':866' 
-- Equation name is '_LC8_C1', type is buried 
_LC8_C1  = LCELL( _EQ088);
  _EQ088 = !_LC3_C3 & !_LC3_C14 &  _LC7_C1
         # !_LC3_C3 & !_LC3_C14 &  _LC4_C3;

-- Node name is '~930~1' 
-- Equation name is '~930~1', location is LC1_C5, type is buried.
-- synthesized logic cell 
!_LC1_C5 = _LC1_C5~NOT;
_LC1_C5~NOT = LCELL( _EQ089);
  _EQ089 = !_LC3_C3 &  _LC6_C1;

-- Node name is ':933' 
-- Equation name is '_LC5_C8', type is buried 
_LC5_C8  = LCELL( _EQ090);
  _EQ090 =  _LC1_C8 & !_LC2_C3
         # !_LC2_C3 &  _LC5_C3
         #  _LC1_C5;

-- Node name is ':934' 
-- Equation name is '_LC5_C12', type is buried 
_LC5_C12 = LCELL( _EQ091);
  _EQ091 =  _LC2_C8 &  _LC2_C12 & !_LC3_C14
         #  _LC1_C5 & !_LC3_C14;

-- Node name is '~935~1' 
-- Equation name is '~935~1', location is LC6_C8, type is buried.
-- synthesized logic cell 
_LC6_C8  = LCELL( _EQ092);
  _EQ092 = !_LC1_C5 & !_LC3_C14;

-- Node name is ':935' 
-- Equation name is '_LC4_C12', type is buried 
_LC4_C12 = LCELL( _EQ093);
  _EQ093 = !_LC5_C3 &  _LC6_C8 &  _LC7_C12
         #  _LC2_C3 &  _LC6_C8;

-- Node name is '~936~1' 
-- Equation name is '~936~1', location is LC6_C1, type is buried.
-- synthesized logic cell 
!_LC6_C1 = _LC6_C1~NOT;
_LC6_C1~NOT = LCELL( _EQ094);
  _EQ094 =  _LC4_C3
         #  _LC1_C3;

-- Node name is ':957' 
-- Equation name is '_LC1_C12', type is buried 
!_LC1_C12 = _LC1_C12~NOT;
_LC1_C12~NOT = LCELL( _EQ095);
  _EQ095 =  _LC2_C12
         #  _LC7_C12
         #  _LC4_C8
         #  _LC1_C8;

-- Node name is ':986' 
-- Equation name is '_LC7_C8', type is buried 
_LC7_C8  = LCELL( _EQ096);
  _EQ096 =  _LC1_C8 & !_LC1_C12 &  _LC3_C14 &  _LC4_C8
         # !_LC1_C8 & !_LC1_C12 &  _LC3_C14 & !_LC4_C8;

-- Node name is ':992' 
-- Equation name is '_LC2_C12', type is buried 
_LC2_C12 = DFFE( _EQ097,  hz1,  VCC,  VCC,  VCC);
  _EQ097 =  _LC5_C12
         #  _LC3_C4 & !_LC6_C12
         #  _LC1_C12 &  _LC3_C4;

-- Node name is ':993' 
-- Equation name is '_LC7_C12', type is buried 
_LC7_C12 = DFFE( _EQ098,  hz1,  VCC,  VCC,  VCC);
  _EQ098 = !_LC1_C12 & !_LC3_C12 &  _LC3_C14
         #  _LC4_C12;

-- Node name is ':994' 
-- Equation name is '_LC4_C8', type is buried 
_LC4_C8  = DFFE( _EQ099,  hz1,  VCC,  VCC,  VCC);
  _EQ099 =  _LC7_C8
         #  _LC4_C8 &  _LC6_C8
         # !_LC2_C8 &  _LC6_C8;

-- Node name is ':995' 
-- Equation name is '_LC1_C8', type is buried 
_LC1_C8  = DFFE( _EQ100,  hz1,  VCC,  VCC,  VCC);
  _EQ100 = !_LC1_C8 &  _LC3_C4
         # !_LC3_C14 &  _LC5_C8;

-- Node name is ':1010' 
-- Equation name is '_LC8_C4', type is buried 
_LC8_C4  = LCELL( _EQ101);
  _EQ101 =  _LC1_C4 &  _LC5_C4
         #  _LC5_C1 &  _LC5_C4
         # !_LC1_C4 &  _LC1_C12 & !_LC5_C1 & !_LC5_C4
         # !_LC1_C12 &  _LC5_C4;

-- Node name is '~1021~1' 
-- Equation name is '~1021~1', location is LC3_C4, type is buried.
-- synthesized logic cell 
_LC3_C4  = LCELL( _EQ102);
  _EQ102 = !_LC1_C12 &  _LC3_C14
         #  _LC3_C8 &  _LC3_C14
         #  _LC2_C4 &  _LC3_C14;

-- Node name is ':1021' 
-- Equation name is '_LC8_C8', type is buried 
_LC8_C8  = LCELL( _EQ103);
  _EQ103 =  _LC2_C4 &  _LC3_C8 &  _LC3_C14
         # !_LC1_C12 &  _LC3_C8 &  _LC3_C14;

-- Node name is ':1023' 
-- Equation name is '_LC4_C4', type is buried 
_LC4_C4  = LCELL( _EQ104);
  _EQ104 =  _LC1_C4 &  _LC3_C4 &  _LC5_C1
         # !_LC1_C4 &  _LC1_C12 &  _LC3_C4 & !_LC5_C1
         #  _LC1_C4 & !_LC1_C12 &  _LC3_C4;

-- Node name is ':1029' 
-- Equation name is '_LC3_C8', type is buried 
_LC3_C8  = DFFE( _EQ105,  hz1,  VCC,  VCC,  VCC);
  _EQ105 =  _LC8_C8
         #  _LC2_C8 &  _LC3_C8 &  _LC6_C8;

-- Node name is ':1030' 
-- Equation name is '_LC5_C4', type is buried 
_LC5_C4  = DFFE( _EQ106,  hz1,  VCC,  VCC,  VCC);
  _EQ106 = !_LC3_C14 &  _LC7_C4
         #  _LC3_C4 &  _LC8_C4;

-- Node name is ':1031' 
-- Equation name is '_LC1_C4', type is buried 
_LC1_C4  = DFFE( _EQ107,  hz1,  VCC,  VCC,  VCC);
  _EQ107 =  _LC4_C4
         # !_LC3_C3 & !_LC3_C14 &  _LC6_C4;

-- Node name is ':1032' 
-- Equation name is '_LC5_C1', type is buried 
_LC5_C1  = DFFE( _EQ108,  hz1,  VCC,  VCC,  VCC);
  _EQ108 =  _LC8_C1
         # !_LC1_C12 &  _LC3_C4 &  _LC5_C1
         #  _LC1_C12 &  _LC3_C4 & !_LC5_C1;



Project Information                          f:\作业\ic\washmachine\wsm321.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:04


Memory Allocated
-----------------

Peak memory allocated during compilation  = 13,983K