📄 wsm319.rpt
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-- Node name is '~504~1'
-- Equation name is '~504~1', location is LC7_A13, type is buried.
-- synthesized logic cell
_LC7_A13 = LCELL( _EQ013);
_EQ013 = !s
# W;
-- Node name is ':506'
-- Equation name is '_LC3_A13', type is buried
_LC3_A13 = DFFE( _EQ014, hz1, VCC, VCC, ee);
_EQ014 = _LC8_A13
# _LC3_A13 & _LC7_A13;
-- Node name is ':516'
-- Equation name is '_LC8_A21', type is buried
_LC8_A21 = DFFE( _EQ015, hz1, VCC, VCC, ee);
_EQ015 = _LC8_A21
# k1;
-- Node name is '~521~1'
-- Equation name is '~521~1', location is LC1_A13, type is buried.
-- synthesized logic cell
_LC1_A13 = LCELL( _EQ016);
_EQ016 = !px & st;
-- Node name is ':529'
-- Equation name is '_LC3_A24', type is buried
_LC3_A24 = LCELL( _EQ017);
_EQ017 = _LC2_A24
# k2;
-- Node name is ':533'
-- Equation name is '_LC2_A24', type is buried
_LC2_A24 = DFFE( _EQ018, hz1, VCC, VCC, ee);
_EQ018 = _LC3_A24 & W
# _LC1_A13 & !W;
-- Node name is ':550'
-- Equation name is '_LC1_A24', type is buried
_LC1_A24 = DFFE( W, hz1, VCC, VCC, ee);
-- Node name is ':585'
-- Equation name is '_LC8_A11', type is buried
_LC8_A11 = LCELL( _EQ019);
_EQ019 = kk
# !_LC6_A5;
-- Node name is ':659'
-- Equation name is '_LC4_A1', type is buried
_LC4_A1 = LCELL( _EQ020);
_EQ020 = !k2 & _LC8_A1
# k1 & !k2
# k3;
-- Node name is ':661'
-- Equation name is '_LC2_A4', type is buried
_LC2_A4 = LCELL( _EQ021);
_EQ021 = !k1 & _LC4_A4
# k2
# k3;
-- Node name is ':663'
-- Equation name is '_LC2_A9', type is buried
_LC2_A9 = LCELL( _EQ022);
_EQ022 = _LC1_A11
# !_LC8_A5
# k3;
-- Node name is '~664~1'
-- Equation name is '~664~1', location is LC8_A5, type is buried.
-- synthesized logic cell
!_LC8_A5 = _LC8_A5~NOT;
_LC8_A5~NOT = LCELL( _EQ023);
_EQ023 = k1
# k2;
-- Node name is '~664~2'
-- Equation name is '~664~2', location is LC6_A5, type is buried.
-- synthesized logic cell
!_LC6_A5 = _LC6_A5~NOT;
_LC6_A5~NOT = LCELL( _EQ024);
_EQ024 = !_LC8_A5
# k3
# k4;
-- Node name is ':666'
-- Equation name is '_LC6_A1', type is buried
_LC6_A1 = LCELL( _EQ025);
_EQ025 = !k3 & !k4 & _LC1_A1
# !k3 & !k4 & !_LC8_A5;
-- Node name is ':668'
-- Equation name is '_LC7_A4', type is buried
_LC7_A4 = LCELL( _EQ026);
_EQ026 = !k4 & _LC5_A4 & _LC8_A5
# k3 & !k4;
-- Node name is ':670'
-- Equation name is '_LC5_A5', type is buried
_LC5_A5 = LCELL( _EQ027);
_EQ027 = !k1 & !k3 & _LC2_A5
# k2 & !k3;
-- Node name is ':680'
-- Equation name is '_LC3_A11', type is buried
!_LC3_A11 = _LC3_A11~NOT;
_LC3_A11~NOT = LCELL( _EQ028);
_EQ028 = _LC5_A11
# _LC3_A1;
-- Node name is '~716~1'
-- Equation name is '~716~1', location is LC7_A11, type is buried.
-- synthesized logic cell
_LC7_A11 = LCELL( _EQ029);
_EQ029 = _LC5_A11 & _LC8_A11
# _LC3_A1 & _LC8_A11;
-- Node name is ':716'
-- Equation name is '_LC6_A11', type is buried
_LC6_A11 = LCELL( _EQ030);
_EQ030 = _LC3_A1 & _LC5_A11 & _LC6_A5 & _LC7_A11
# !_LC3_A1 & !_LC5_A11 & _LC7_A11
# !_LC3_A1 & !_LC6_A5 & _LC7_A11;
-- Node name is ':717'
-- Equation name is '_LC7_A5', type is buried
_LC7_A5 = LCELL( _EQ031);
_EQ031 = _LC2_A1 & _LC3_A5 & _LC6_A5 & _LC7_A11
# !_LC2_A1 & !_LC3_A5 & _LC7_A11
# !_LC2_A1 & !_LC6_A5 & _LC7_A11;
-- Node name is ':718'
-- Equation name is '_LC7_A1', type is buried
_LC7_A1 = LCELL( _EQ032);
_EQ032 = _LC6_A1 & _LC7_A11 & _LC8_A1
# _LC3_A4 & _LC6_A1 & _LC7_A11
# !_LC3_A4 & !_LC6_A1 & _LC7_A11 & !_LC8_A1;
-- Node name is ':719'
-- Equation name is '_LC5_A1', type is buried
_LC5_A1 = LCELL( _EQ033);
_EQ033 = !k4 & _LC3_A4 & _LC4_A1 & _LC7_A11
# !_LC3_A4 & !_LC4_A1 & _LC7_A11
# k4 & !_LC3_A4 & _LC7_A11;
-- Node name is ':720'
-- Equation name is '_LC8_A4', type is buried
_LC8_A4 = LCELL( _EQ034);
_EQ034 = _LC4_A4 & _LC7_A4 & _LC7_A11
# _LC1_A4 & _LC7_A4 & _LC7_A11
# !_LC1_A4 & !_LC4_A4 & !_LC7_A4 & _LC7_A11;
-- Node name is ':721'
-- Equation name is '_LC6_A4', type is buried
_LC6_A4 = LCELL( _EQ035);
_EQ035 = !k4 & _LC1_A4 & _LC2_A4 & _LC7_A11
# !_LC1_A4 & !_LC2_A4 & _LC7_A11
# k4 & !_LC1_A4 & _LC7_A11;
-- Node name is ':722'
-- Equation name is '_LC4_A5', type is buried
_LC4_A5 = LCELL( _EQ036);
_EQ036 = k4 & _LC7_A11
# _LC2_A9 & _LC5_A5 & _LC7_A11
# !_LC2_A9 & !_LC5_A5 & _LC7_A11;
-- Node name is ':742'
-- Equation name is '_LC5_A11', type is buried
_LC5_A11 = DFFE( _EQ037, hz1, VCC, VCC, ee);
_EQ037 = _LC6_A11
# _LC5_A11 & !_LC8_A11;
-- Node name is ':743'
-- Equation name is '_LC3_A5', type is buried
_LC3_A5 = DFFE( _EQ038, hz1, VCC, VCC, ee);
_EQ038 = _LC7_A5
# _LC3_A5 & !_LC8_A11;
-- Node name is ':744'
-- Equation name is '_LC1_A1', type is buried
_LC1_A1 = DFFE( _EQ039, hz1, VCC, VCC, ee);
_EQ039 = _LC7_A1
# _LC1_A1 & !_LC8_A11;
-- Node name is ':745'
-- Equation name is '_LC8_A1', type is buried
_LC8_A1 = DFFE( _EQ040, hz1, VCC, VCC, ee);
_EQ040 = _LC5_A1
# _LC8_A1 & !_LC8_A11;
-- Node name is ':746'
-- Equation name is '_LC5_A4', type is buried
_LC5_A4 = DFFE( _EQ041, hz1, VCC, VCC, ee);
_EQ041 = _LC8_A4
# _LC5_A4 & !_LC8_A11;
-- Node name is ':747'
-- Equation name is '_LC4_A4', type is buried
_LC4_A4 = DFFE( _EQ042, hz1, VCC, VCC, ee);
_EQ042 = _LC6_A4
# _LC4_A4 & !_LC8_A11;
-- Node name is ':748'
-- Equation name is '_LC2_A5', type is buried
_LC2_A5 = DFFE( _EQ043, hz1, VCC, VCC, ee);
_EQ043 = _LC4_A5
# _LC2_A5 & !_LC8_A11;
-- Node name is ':749'
-- Equation name is '_LC1_A11', type is buried
_LC1_A11 = DFFE( _EQ044, hz1, VCC, VCC, ee);
_EQ044 = _LC4_A11
# _LC2_A9 & !_LC8_A11;
Project Information e:\washmachine\wsm319.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 14,113K
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