📄 wsm319.rpt
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** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
21 - - B -- OUTPUT 0 1 0 0 cn0
22 - - B -- OUTPUT 0 1 0 0 cn1
23 - - B -- OUTPUT 0 1 0 0 cn2
24 - - B -- OUTPUT 0 1 0 0 cn3
25 - - B -- OUTPUT 0 1 0 0 cn4
27 - - C -- OUTPUT 0 1 0 0 cn5
28 - - C -- OUTPUT 0 1 0 0 cn6
29 - - C -- OUTPUT 0 1 0 0 cn7
81 - - - 22 OUTPUT 0 1 0 0 l1
80 - - - 23 OUTPUT 0 1 0 0 l2
79 - - - 24 OUTPUT 0 1 0 0 l3
83 - - - 13 OUTPUT 0 1 0 0 sound
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\washmachine\wsm319.rpt
wsm319
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - A 21 AND2 s 3 0 0 2 key1~1
- 1 - A 04 OR2 0 3 0 3 |lpm_add_sub:767|addcore:adder|pcarry1
- 3 - A 04 OR2 0 3 0 4 |lpm_add_sub:767|addcore:adder|pcarry3
- 2 - A 01 OR2 0 3 0 1 |lpm_add_sub:767|addcore:adder|pcarry5
- 3 - A 01 OR2 0 4 0 3 |lpm_add_sub:767|addcore:adder|pcarry6
- 2 - A 21 DFFE 4 0 0 7 k3 (:49)
- 1 - A 05 DFFE 3 0 0 5 k2 (:61)
- 1 - A 21 DFFE 2 0 0 5 k1 (:66)
- 3 - A 21 DFFE 2 1 0 8 k4 (:101)
- 5 - A 13 DFFE 3 1 0 16 ee (:312)
- 4 - A 13 DFFE 1 2 0 1 px (:317)
- 6 - A 13 DFFE 1 1 0 2 st (:336)
- 8 - A 13 AND2 s 1 2 0 1 W~1 (~455~1)
- 2 - A 13 DFFE 1 1 0 4 W (:455)
- 7 - A 13 OR2 s 1 1 0 2 ~504~1
- 3 - A 13 DFFE 1 3 1 0 :506
- 8 - A 21 DFFE 1 2 1 0 :516
- 1 - A 13 AND2 s 0 2 0 1 ~521~1
- 3 - A 24 OR2 0 2 0 1 :529
- 2 - A 24 DFFE 1 4 1 1 :533
- 1 - A 24 DFFE 1 2 1 0 :550
- 4 - A 11 AND2 s 0 4 0 1 kk~1 (~576~1)
- 2 - A 11 DFFE 1 2 0 2 kk (:576)
- 8 - A 11 OR2 0 2 0 10 :585
- 4 - A 01 OR2 0 4 0 1 :659
- 2 - A 04 OR2 0 4 0 1 :661
- 2 - A 09 OR2 0 3 0 4 :663
- 8 - A 05 OR2 s ! 0 2 0 4 ~664~1
- 6 - A 05 OR2 s ! 0 3 0 3 ~664~2
- 6 - A 01 OR2 0 4 0 1 :666
- 7 - A 04 OR2 0 4 0 1 :668
- 5 - A 05 OR2 0 4 0 2 :670
- 3 - A 11 OR2 ! 0 2 0 1 :680
- 7 - A 11 OR2 s 0 3 0 7 ~716~1
- 6 - A 11 OR2 0 4 0 1 :716
- 7 - A 05 OR2 0 4 0 1 :717
- 7 - A 01 OR2 0 4 0 1 :718
- 5 - A 01 OR2 0 4 0 1 :719
- 8 - A 04 OR2 0 4 0 1 :720
- 6 - A 04 OR2 0 4 0 1 :721
- 4 - A 05 OR2 0 4 0 1 :722
- 5 - A 11 DFFE 1 3 1 3 :742
- 3 - A 05 DFFE 1 3 1 2 :743
- 1 - A 01 DFFE 1 3 1 3 :744
- 8 - A 01 DFFE 1 3 1 4 :745
- 5 - A 04 DFFE 1 3 1 2 :746
- 4 - A 04 DFFE 1 3 1 3 :747
- 2 - A 05 DFFE 1 3 1 1 :748
- 1 - A 11 DFFE 1 4 1 1 :749
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\washmachine\wsm319.rpt
wsm319
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 15/ 96( 15%) 13/ 48( 27%) 3/ 48( 6%) 3/16( 18%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 5/ 48( 10%) 0/ 48( 0%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
C: 0/ 96( 0%) 3/ 48( 6%) 0/ 48( 0%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 3/24( 12%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
02: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 4/24( 16%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\washmachine\wsm319.rpt
wsm319
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 16 hz1
INPUT 6 hz1k
Device-Specific Information: e:\washmachine\wsm319.rpt
wsm319
** EQUATIONS **
hz1 : INPUT;
hz1k : INPUT;
key1 : INPUT;
key2 : INPUT;
key3 : INPUT;
key4 : INPUT;
s : INPUT;
start : INPUT;
-- Node name is 'cn0'
-- Equation name is 'cn0', type is output
cn0 = _LC1_A11;
-- Node name is 'cn1'
-- Equation name is 'cn1', type is output
cn1 = _LC2_A5;
-- Node name is 'cn2'
-- Equation name is 'cn2', type is output
cn2 = _LC4_A4;
-- Node name is 'cn3'
-- Equation name is 'cn3', type is output
cn3 = _LC5_A4;
-- Node name is 'cn4'
-- Equation name is 'cn4', type is output
cn4 = _LC8_A1;
-- Node name is 'cn5'
-- Equation name is 'cn5', type is output
cn5 = _LC1_A1;
-- Node name is 'cn6'
-- Equation name is 'cn6', type is output
cn6 = _LC3_A5;
-- Node name is 'cn7'
-- Equation name is 'cn7', type is output
cn7 = _LC5_A11;
-- Node name is ':312' = 'ee'
-- Equation name is 'ee', location is LC5_A13, type is buried.
ee = DFFE( _EQ001, hz1k, VCC, VCC, VCC);
_EQ001 = ee & key4
# ee & !_LC4_A21
# !key4 & _LC4_A21 & start;
-- Node name is 'key1~1'
-- Equation name is 'key1~1', location is LC4_A21, type is buried.
-- synthesized logic cell
_LC4_A21 = LCELL( _EQ002);
_EQ002 = !key1 & !key2 & !key3;
-- Node name is ':576' = 'kk'
-- Equation name is 'kk', location is LC2_A11, type is buried.
kk = DFFE( _LC8_A11, hz1, VCC, VCC, ee);
-- Node name is '~576~1' = 'kk~1'
-- Equation name is '~576~1', location is LC4_A11, type is buried.
-- synthesized logic cell
_LC4_A11 = LCELL( _EQ003);
_EQ003 = kk & !k4 & !_LC2_A9 & !_LC3_A11;
-- Node name is ':66' = 'k1'
-- Equation name is 'k1', location is LC1_A21, type is buried.
k1 = DFFE( VCC, hz1k, VCC, VCC, key1);
-- Node name is ':61' = 'k2'
-- Equation name is 'k2', location is LC1_A5, type is buried.
k2 = DFFE( _EQ004, hz1k, VCC, VCC, VCC);
_EQ004 = k2
# !key1 & key2;
-- Node name is ':49' = 'k3'
-- Equation name is 'k3', location is LC2_A21, type is buried.
k3 = DFFE( _EQ005, hz1k, VCC, VCC, VCC);
_EQ005 = k3
# !key1 & !key2 & key3;
-- Node name is ':101' = 'k4'
-- Equation name is 'k4', location is LC3_A21, type is buried.
k4 = DFFE( _EQ006, hz1k, VCC, VCC, VCC);
_EQ006 = k4
# key4 & _LC4_A21;
-- Node name is 'l1'
-- Equation name is 'l1', type is output
l1 = _LC8_A21;
-- Node name is 'l2'
-- Equation name is 'l2', type is output
l2 = _LC2_A24;
-- Node name is 'l3'
-- Equation name is 'l3', type is output
l3 = _LC1_A24;
-- Node name is ':317' = 'px'
-- Equation name is 'px', location is LC4_A13, type is buried.
px = DFFE( _EQ007, hz1, VCC, VCC, ee);
_EQ007 = px & W;
-- Node name is 'sound'
-- Equation name is 'sound', type is output
sound = _LC3_A13;
-- Node name is ':336' = 'st'
-- Equation name is 'st', location is LC6_A13, type is buried.
st = DFFE( st, hz1, VCC, VCC, ee);
-- Node name is ':455' = 'W'
-- Equation name is 'W', location is LC2_A13, type is buried.
W = DFFE( W, hz1, VCC, VCC, ee);
-- Node name is '~455~1' = 'W~1'
-- Equation name is '~455~1', location is LC8_A13, type is buried.
-- synthesized logic cell
_LC8_A13 = LCELL( _EQ008);
_EQ008 = hz1k & !_LC7_A13 & !st;
-- Node name is '|lpm_add_sub:767|addcore:adder|pcarry1' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC1_A4', type is buried
_LC1_A4 = LCELL( _EQ009);
_EQ009 = _LC5_A5
# k4
# _LC2_A9;
-- Node name is '|lpm_add_sub:767|addcore:adder|pcarry3' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC3_A4', type is buried
_LC3_A4 = LCELL( _EQ010);
_EQ010 = _LC5_A4
# _LC4_A4
# _LC1_A4;
-- Node name is '|lpm_add_sub:767|addcore:adder|pcarry5' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC2_A1', type is buried
_LC2_A1 = LCELL( _EQ011);
_EQ011 = _LC8_A1
# _LC3_A4
# _LC1_A1;
-- Node name is '|lpm_add_sub:767|addcore:adder|pcarry6' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC3_A1', type is buried
_LC3_A1 = LCELL( _EQ012);
_EQ012 = _LC3_A5
# _LC1_A1
# _LC8_A1
# _LC3_A4;
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