📄 xiaolizi1588.map.qmsg
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{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 xiaolizi1588.v(87) " "Warning: Verilog HDL assignment warning at xiaolizi1588.v(87): truncated value with size 32 to match size of target (1)" { } { { "../xiaolizi1588.v" "" { Text "E:/xiaolizi1588/xiaolizi1588.v" 87 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 xiaolizi1588.v(92) " "Warning: Verilog HDL assignment warning at xiaolizi1588.v(92): truncated value with size 32 to match size of target (4)" { } { { "../xiaolizi1588.v" "" { Text "E:/xiaolizi1588/xiaolizi1588.v" 92 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 xiaolizi1588.v(95) " "Warning: Verilog HDL assignment warning at xiaolizi1588.v(95): truncated value with size 32 to match size of target (4)" { } { { "../xiaolizi1588.v" "" { Text "E:/xiaolizi1588/xiaolizi1588.v" 95 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 xiaolizi1588.v(96) " "Warning: Verilog HDL assignment warning at xiaolizi1588.v(96): truncated value with size 32 to match size of target (1)" { } { { "../xiaolizi1588.v" "" { Text "E:/xiaolizi1588/xiaolizi1588.v" 96 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 xiaolizi1588.v(99) " "Warning: Verilog HDL assignment warning at xiaolizi1588.v(99): truncated value with size 32 to match size of target (4)" { } { { "../xiaolizi1588.v" "" { Text "E:/xiaolizi1588/xiaolizi1588.v" 99 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 xiaolizi1588.v(102) " "Warning: Verilog HDL assignment warning at xiaolizi1588.v(102): truncated value with size 32 to match size of target (4)" { } { { "../xiaolizi1588.v" "" { Text "E:/xiaolizi1588/xiaolizi1588.v" 102 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 xiaolizi1588.v(105) " "Warning: Verilog HDL assignment warning at xiaolizi1588.v(105): truncated value with size 32 to match size of target (4)" { } { { "../xiaolizi1588.v" "" { Text "E:/xiaolizi1588/xiaolizi1588.v" 105 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 xiaolizi1588.v(108) " "Warning: Verilog HDL assignment warning at xiaolizi1588.v(108): truncated value with size 32 to match size of target (4)" { } { { "../xiaolizi1588.v" "" { Text "E:/xiaolizi1588/xiaolizi1588.v" 108 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 xiaolizi1588.v(109) " "Warning: Verilog HDL assignment warning at xiaolizi1588.v(109): truncated value with size 32 to match size of target (3)" { } { { "../xiaolizi1588.v" "" { Text "E:/xiaolizi1588/xiaolizi1588.v" 109 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 xiaolizi1588.v(112) " "Warning: Verilog HDL assignment warning at xiaolizi1588.v(112): truncated value with size 32 to match size of target (4)" { } { { "../xiaolizi1588.v" "" { Text "E:/xiaolizi1588/xiaolizi1588.v" 112 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 xiaolizi1588.v(115) " "Warning: Verilog HDL assignment warning at xiaolizi1588.v(115): truncated value with size 32 to match size of target (4)" { } { { "../xiaolizi1588.v" "" { Text "E:/xiaolizi1588/xiaolizi1588.v" 115 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "xiaolizi1588.v(49) " "Warning: (10270) Verilog HDL statement warning at xiaolizi1588.v(49): incomplete Case Statement has no default case item" { } { { "../xiaolizi1588.v" "" { Text "E:/xiaolizi1588/xiaolizi1588.v" 49 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 xiaolizi1588.v(118) " "Warning: Verilog HDL assignment warning at xiaolizi1588.v(118): truncated value with size 32 to match size of target (1)" { } { { "../xiaolizi1588.v" "" { Text "E:/xiaolizi1588/xiaolizi1588.v" 118 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 9 xiaolizi1588.v(120) " "Warning: Verilog HDL assignment warning at xiaolizi1588.v(120): truncated value with size 32 to match size of target (9)" { } { { "../xiaolizi1588.v" "" { Text "E:/xiaolizi1588/xiaolizi1588.v" 120 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 xiaolizi1588.v(121) " "Warning: Verilog HDL assignment warning at xiaolizi1588.v(121): truncated value with size 32 to match size of target (1)" { } { { "../xiaolizi1588.v" "" { Text "E:/xiaolizi1588/xiaolizi1588.v" 121 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 xiaolizi1588.v(122) " "Warning: Verilog HDL assignment warning at xiaolizi1588.v(122): truncated value with size 32 to match size of target (1)" { } { { "../xiaolizi1588.v" "" { Text "E:/xiaolizi1588/xiaolizi1588.v" 122 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 xiaolizi1588.v(123) " "Warning: Verilog HDL assignment warning at xiaolizi1588.v(123): truncated value with size 32 to match size of target (1)" { } { { "../xiaolizi1588.v" "" { Text "E:/xiaolizi1588/xiaolizi1588.v" 123 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 xiaolizi1588.v(131) " "Warning: Verilog HDL assignment warning at xiaolizi1588.v(131): truncated value with size 32 to match size of target (1)" { } { { "../xiaolizi1588.v" "" { Text "E:/xiaolizi1588/xiaolizi1588.v" 131 0 0 } } } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 xiaolizi1588.v(136) " "Warning: Verilog HDL assignment warning at xiaolizi1588.v(136): truncated value with size 32 to match size of target (1)" { } { { "../xiaolizi1588.v" "" { Text "E:/xiaolizi1588/xiaolizi1588.v" 136 0 0 } } } 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "set High " "Info: Power-up level of register \"set\" is not specified -- using power-up level of High to minimize register" { } { { "../xiaolizi1588.v" "" { Text "E:/xiaolizi1588/xiaolizi1588.v" 20 -1 0 } } } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "set data_in VCC " "Warning: Reduced register \"set\" with stuck data_in port to stuck value VCC" { } { { "../xiaolizi1588.v" "" { Text "E:/xiaolizi1588/xiaolizi1588.v" 20 -1 0 } } } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" { } { { "lpm_add_sub.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" { } { { "addcore.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/addcore.tdf" 73 1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" { } { { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" { } { { "altshift.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altshift.tdf" 28 1 0 } } } 0} } { } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 43 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 43 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 13 21:26:43 2006 " "Info: Processing ended: Thu Apr 13 21:26:43 2006" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" { } { } 0} } { } 0}
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