xiaolizi1588.map.rpt

ic读卡器 能读ic电话卡并按时记费

; Total logic elements              ; 162     ;
; Total combinational functions     ; 160     ;
;     -- Total 4-input functions    ; 60      ;
;     -- Total 3-input functions    ; 13      ;
;     -- Total 2-input functions    ; 23      ;
;     -- Total 1-input functions    ; 64      ;
;     -- Total 0-input functions    ; 0       ;
; Combinational cells for routing   ; 0       ;
; Total registers                   ; 88      ;
; Total logic cells in carry chains ; 64      ;
; I/O pins                          ; 29      ;
; Maximum fan-out node              ; clk     ;
; Maximum fan-out                   ; 88      ;
; Total fan-out                     ; 642     ;
; Average fan-out                   ; 3.36    ;
+-----------------------------------+---------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                        ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; |xiaolizi1588              ; 162 (162)   ; 88           ; 0           ; 0            ; 0       ; 0         ; 0         ; 29   ; 0            ; 74 (74)      ; 2 (2)             ; 86 (86)          ; 64 (64)         ; |xiaolizi1588       ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 88    ;
; Number of registers using Synchronous Clear  ; 64    ;
; Number of registers using Synchronous Load   ; 1     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 11    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 32 bits   ; 64 LEs        ; 32 LEs               ; 32 LEs                 ; Yes        ; |xiaolizi1588|numl[30]     ;
; 4:1                ; 32 bits   ; 64 LEs        ; 32 LEs               ; 32 LEs                 ; Yes        ; |xiaolizi1588|temp[9]      ;
; 12:1               ; 4 bits    ; 32 LEs        ; 4 LEs                ; 28 LEs                 ; Yes        ; |xiaolizi1588|money[7]     ;
; 12:1               ; 3 bits    ; 24 LEs        ; 0 LEs                ; 24 LEs                 ; Yes        ; |xiaolizi1588|money[10]    ;
; 12:1               ; 4 bits    ; 32 LEs        ; 4 LEs                ; 28 LEs                 ; Yes        ; |xiaolizi1588|dtime[0]     ;
; 13:1               ; 4 bits    ; 32 LEs        ; 4 LEs                ; 28 LEs                 ; Yes        ; |xiaolizi1588|dtime[4]     ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/xiaolizi1588/xiaolizi1588/xiaolizi1588.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Thu Apr 13 21:25:30 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off xiaolizi1588 -c xiaolizi1588
Info: Found 1 design units, including 1 entities, in source file ../xiaolizi1588.v
    Info: Found entity 1: xiaolizi1588
Info: Elaborating entity "xiaolizi1588" for the top level hierarchy
Warning: Verilog HDL assignment warning at xiaolizi1588.v(23): truncated value with size 32 to match size of target (11)
Warning: Verilog HDL assignment warning at xiaolizi1588.v(27): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at xiaolizi1588.v(32): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at xiaolizi1588.v(38): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at xiaolizi1588.v(45): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at xiaolizi1588.v(52): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at xiaolizi1588.v(53): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at xiaolizi1588.v(54): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at xiaolizi1588.v(59): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at xiaolizi1588.v(61): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at xiaolizi1588.v(62): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at xiaolizi1588.v(63): truncated value with size 32 to match size of target (3)
Warning: Verilog HDL assignment warning at xiaolizi1588.v(66): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at xiaolizi1588.v(67): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at xiaolizi1588.v(70): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at xiaolizi1588.v(72): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at xiaolizi1588.v(73): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at xiaolizi1588.v(75): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at xiaolizi1588.v(78): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at xiaolizi1588.v(79): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at xiaolizi1588.v(80): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at xiaolizi1588.v(85): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at xiaolizi1588.v(86): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at xiaolizi1588.v(87): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at xiaolizi1588.v(92): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at xiaolizi1588.v(95): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at xiaolizi1588.v(96): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at xiaolizi1588.v(99): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at xiaolizi1588.v(102): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at xiaolizi1588.v(105): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at xiaolizi1588.v(108): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at xiaolizi1588.v(109): truncated value with size 32 to match size of target (3)
Warning: Verilog HDL assignment warning at xiaolizi1588.v(112): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at xiaolizi1588.v(115): truncated value with size 32 to match size of target (4)
Warning: (10270) Verilog HDL statement warning at xiaolizi1588.v(49): incomplete Case Statement has no default case item
Warning: Verilog HDL assignment warning at xiaolizi1588.v(118): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at xiaolizi1588.v(120): truncated value with size 32 to match size of target (9)
Warning: Verilog HDL assignment warning at xiaolizi1588.v(121): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at xiaolizi1588.v(122): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at xiaolizi1588.v(123): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at xiaolizi1588.v(131): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at xiaolizi1588.v(136): truncated value with size 32 to match size of target (1)
Info: Power-up level of register "set" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "set" with stuck data_in port to stuck value VCC
Info: Duplicate registers merged to single register
    Info: Duplicate register "reset_ena" merged to single register "warn~reg0"
Info: Implemented 191 device resources after synthesis - the final resource count might be different
    Info: Implemented 5 input pins
    Info: Implemented 24 output pins
    Info: Implemented 162 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 43 warnings
    Info: Processing ended: Thu Apr 13 21:25:35 2006
    Info: Elapsed time: 00:00:06