📄 p2s.rpt
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G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\test\p2s.rpt
p2s
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
15 29 B FF t 0 0 0 1 2 1 0 LCD0
16 27 B FF t 0 0 0 1 3 1 0 LCD1
17 25 B FF t 0 0 0 1 3 1 0 LCD2
18 24 B FF t 0 0 0 1 3 1 0 LCD3
20 21 B FF t 0 0 0 1 2 1 0 LCD4
21 19 B FF t 0 0 0 1 2 1 0 LCD5
22 17 B FF t 0 0 0 1 3 1 0 LCD6
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\test\p2s.rpt
p2s
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 103 G SOFT t 0 0 0 0 8 0 5 |LPM_ADD_SUB:287|addcore:adder|addcore:adder0|cout_node
(70) 109 G SOFT t 0 0 0 0 2 0 1 |LPM_ADD_SUB:287|addcore:adder|addcore:adder0|result_node1
(64) 99 G SOFT t 0 0 0 0 4 0 1 |LPM_ADD_SUB:287|addcore:adder|addcore:adder0|result_node3
- 102 G SOFT t 0 0 0 0 5 0 1 |LPM_ADD_SUB:287|addcore:adder|addcore:adder0|result_node4
(69) 107 G SOFT t 0 0 0 0 6 0 1 |LPM_ADD_SUB:287|addcore:adder|addcore:adder0|result_node5
- 110 G SOFT t 0 0 0 0 7 0 1 |LPM_ADD_SUB:287|addcore:adder|addcore:adder0|result_node6
- 108 G SOFT t 0 0 0 0 8 0 1 |LPM_ADD_SUB:287|addcore:adder|addcore:adder0|result_node7
- 122 H SOFT t 0 0 0 0 16 0 8 |LPM_ADD_SUB:287|addcore:adder|addcore:adder1|cout_node
- 127 H SOFT t 0 0 0 0 9 0 1 |LPM_ADD_SUB:287|addcore:adder|addcore:adder1|result_node0
(75) 118 H SOFT t 0 0 0 0 12 0 1 |LPM_ADD_SUB:287|addcore:adder|addcore:adder1|result_node3
- 114 H SOFT t 0 0 0 0 13 0 1 |LPM_ADD_SUB:287|addcore:adder|addcore:adder1|result_node4
- 113 H SOFT t 0 0 0 0 14 0 1 |LPM_ADD_SUB:287|addcore:adder|addcore:adder1|result_node5
(77) 123 H SOFT t 0 0 0 0 15 0 1 |LPM_ADD_SUB:287|addcore:adder|addcore:adder1|result_node6
(76) 120 H SOFT t 0 0 0 0 16 0 1 |LPM_ADD_SUB:287|addcore:adder|addcore:adder1|result_node7
- 7 A SOFT t 0 0 0 0 17 0 3 |LPM_ADD_SUB:287|addcore:adder|addcore:adder2|cout_node
- 116 H SOFT t 0 0 0 0 17 0 1 |LPM_ADD_SUB:287|addcore:adder|addcore:adder2|result_node0
- 15 A SOFT t 0 0 0 0 13 0 1 |LPM_ADD_SUB:287|addcore:adder|addcore:adder2|result_node3
- 10 A SOFT t 0 0 0 0 6 0 1 |LPM_ADD_SUB:287|addcore:adder|addcore:adder2|result_node4
(9) 8 A SOFT t 0 0 0 0 7 0 1 |LPM_ADD_SUB:287|addcore:adder|addcore:adder2|result_node5
(8) 11 A SOFT t 0 0 0 0 8 0 1 |LPM_ADD_SUB:287|addcore:adder|addcore:adder2|result_node6
(11) 5 A SOFT t 0 0 0 0 9 0 1 |LPM_ADD_SUB:287|addcore:adder|addcore:adder2|result_node7
(5) 14 A SOFT t 0 0 0 0 18 0 1 |LPM_ADD_SUB:287|addcore:adder|addcore:adder3|result_node0
- 2 A SOFT t 0 0 0 0 13 0 1 |LPM_ADD_SUB:287|addcore:adder|addcore:adder3|result_node3
(4) 16 A SOFT t 0 0 0 0 6 0 1 |LPM_ADD_SUB:287|addcore:adder|addcore:adder3|result_node4
(10) 6 A SOFT t 0 0 0 0 7 0 1 |LPM_ADD_SUB:287|addcore:adder|addcore:adder3|result_node5
- 4 A SOFT t 0 0 0 0 8 0 1 |LPM_ADD_SUB:287|addcore:adder|addcore:adder3|result_node6
- 12 A SOFT t 0 0 0 0 17 0 1 |LPM_ADD_SUB:287|addcore:adder|addcore:adder3|result_node7
(74) 117 H DFFE + t 0 0 0 0 32 7 8 clk_2 (:21)
- 31 B TFFE t 0 0 0 2 5 0 2 reg3 (:22)
- 20 B TFFE t 0 0 0 2 5 0 2 reg2 (:23)
- 28 B TFFE t 0 0 0 2 5 0 2 reg1 (:24)
- 26 B TFFE t 0 0 0 2 5 0 2 reg0 (:25)
- 18 B DFFE t 4 0 1 1 9 4 1 temp (:26)
- 121 H TFFE + t 0 0 0 0 33 0 34 count31 (:27)
(80) 126 H DFFE + t 0 0 0 0 33 0 28 count30 (:28)
(81) 128 H DFFE + t 0 0 0 0 33 0 29 count29 (:29)
- 119 H DFFE + t 0 0 0 0 33 0 30 count28 (:30)
- 100 G DFFE + t 0 0 0 0 33 0 31 count27 (:31)
(6) 13 A TFFE + t 0 0 0 0 13 0 32 count26 (:32)
- 1 A TFFE + t 0 0 0 0 12 0 33 count25 (:33)
(65) 101 G DFFE + t 0 0 0 0 33 0 34 count24 (:34)
- 98 G DFFE + t 0 0 0 0 33 0 33 count23 (:35)
(63) 97 G DFFE + t 0 0 0 0 33 0 34 count22 (:36)
- 89 F DFFE + t 0 0 0 0 33 0 35 count21 (:37)
- 90 F DFFE + t 0 0 0 0 33 0 36 count20 (:38)
(58) 91 F DFFE + t 0 0 0 0 33 0 37 count19 (:39)
- 9 A TFFE + t 0 0 0 0 13 0 38 count18 (:40)
(12) 3 A TFFE + t 0 0 0 0 12 0 39 count17 (:41)
(60) 93 F DFFE + t 0 0 0 0 33 0 40 count16 (:42)
- 68 E DFFE + t 0 0 0 0 33 0 34 count15 (:43)
(45) 67 E DFFE + t 0 0 0 0 33 0 35 count14 (:44)
(44) 65 E DFFE + t 0 0 0 0 33 0 36 count13 (:45)
- 54 D DFFE + t 0 0 0 0 33 0 37 count12 (:46)
- 50 D DFFE + t 0 0 0 0 33 0 38 count11 (:47)
(73) 115 H TFFE + t 0 0 0 0 12 0 39 count10 (:48)
(79) 125 H TFFE + t 0 0 0 0 11 0 40 count9 (:49)
- 58 D DFFE + t 0 0 0 0 33 0 41 count8 (:50)
- 74 E DFFE + t 0 0 0 0 33 0 38 count7 (:51)
(36) 57 D DFFE + t 0 0 0 0 33 0 39 count6 (:52)
- 42 C DFFE + t 0 0 0 0 33 0 40 count5 (:53)
- 44 C DFFE + t 0 0 0 0 33 0 41 count4 (:54)
- 34 C DFFE + t 0 0 0 0 33 0 42 count3 (:55)
(67) 104 G TFFE + t 0 0 0 0 4 0 43 count2 (:56)
- 33 C DFFE + t 0 0 0 0 33 0 43 count1 (:57)
- 124 H DFFE + t 0 0 0 0 31 0 44 count0 (:58)
- 22 B DFFE t 0 0 0 1 4 0 8 i2 (:545)
- 23 B TFFE t 0 0 0 1 4 0 7 i1 (:546)
- 30 B DFFE t 0 0 0 1 3 0 8 i0 (:547)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\test\p2s.rpt
p2s
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+------------------------------- LC7 |LPM_ADD_SUB:287|addcore:adder|addcore:adder2|cout_node
| +----------------------------- LC15 |LPM_ADD_SUB:287|addcore:adder|addcore:adder2|result_node3
| | +--------------------------- LC10 |LPM_ADD_SUB:287|addcore:adder|addcore:adder2|result_node4
| | | +------------------------- LC8 |LPM_ADD_SUB:287|addcore:adder|addcore:adder2|result_node5
| | | | +----------------------- LC11 |LPM_ADD_SUB:287|addcore:adder|addcore:adder2|result_node6
| | | | | +--------------------- LC5 |LPM_ADD_SUB:287|addcore:adder|addcore:adder2|result_node7
| | | | | | +------------------- LC14 |LPM_ADD_SUB:287|addcore:adder|addcore:adder3|result_node0
| | | | | | | +----------------- LC2 |LPM_ADD_SUB:287|addcore:adder|addcore:adder3|result_node3
| | | | | | | | +--------------- LC16 |LPM_ADD_SUB:287|addcore:adder|addcore:adder3|result_node4
| | | | | | | | | +------------- LC6 |LPM_ADD_SUB:287|addcore:adder|addcore:adder3|result_node5
| | | | | | | | | | +----------- LC4 |LPM_ADD_SUB:287|addcore:adder|addcore:adder3|result_node6
| | | | | | | | | | | +--------- LC12 |LPM_ADD_SUB:287|addcore:adder|addcore:adder3|result_node7
| | | | | | | | | | | | +------- LC13 count26
| | | | | | | | | | | | | +----- LC1 count25
| | | | | | | | | | | | | | +--- LC9 count18
| | | | | | | | | | | | | | | +- LC3 count17
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'A'
LC | | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'A':
LC7 -> - - - - - - - - * * * - - - - - | * - - - - - - - | <-- |LPM_ADD_SUB:287|addcore:adder|addcore:adder2|cout_node
LC13 -> - - - - - - - * * * * * * - - - | * - * * * * * * | <-- count26
LC1 -> - - - - - - - * * * * * * * - - | * - * * * * * * | <-- count25
LC9 -> * * * * * * * * - - - * * * * - | * - * * * * * * | <-- count18
LC3 -> * * * * * * * * - - - * * * * * | * - * * * * * * | <-- count17
Pin
83 -> - - - - - - - - - - - - - - - - | - - - - - - - - | <-- clk
LC103-> * * - - - - * - - - - - - - * * | * - - - - - - - | <-- |LPM_ADD_SUB:287|addcore:adder|addcore:adder0|cout_node
LC122-> - - * * * * - * - - - * * * - - | * - - - - - - - | <-- |LPM_ADD_SUB:287|addcore:adder|addcore:adder1|cout_node
LC121-> - - - - - - - - - - - * * * * * | * - * * * * * * | <-- count31
LC126-> - - - - - - - - - - * * - - - - | * - * * * * * * | <-- count30
LC128-> - - - - - - - - - * * * - - - - | * - * * * * * * | <-- count29
LC119-> - - - - - - - - * * * * - - - - | * - * * * * * * | <-- count28
LC100-> - - - - - - - * * * * * - - - - | * - * * * * * * | <-- count27
LC101-> - - - - - - * * * * * * * * - - | * - * * * * * * | <-- count24
LC98 -> * - - - - * * * - - - * * * - - | * - * * * * * * | <-- count23
LC97 -> * - - - * * * * - - - * * * - - | * - * * * * * * | <-- count22
LC89 -> * - - * * * * * - - - * * * - - | * - * * * * * * | <-- count21
LC90 -> * - * * * * * * - - - * * * - - | * - * * * * * * | <-- count20
LC91 -> * * * * * * * * - - - * * * - - | * - * * * * * * | <-- count19
LC93 -> * * * * * * * * - - - * * * * * | * - * * * * * * | <-- count16
LC68 -> * * - - - - * - - - - - - - * * | * - * * * * * * | <-- count15
LC67 -> * * - - - - * - - - - - - - * * | * - * * * * * * | <-- count14
LC65 -> * * - - - - * - - - - - - - * * | * - * * * * * * | <-- count13
LC54 -> * * - - - - * - - - - - - - * * | * - * * * * * * | <-- count12
LC50 -> * * - - - - * - - - - - - - * * | * - * * * * * * | <-- count11
LC115-> * * - - - - * - - - - - - - * * | * - * * * * * * | <-- count10
LC125-> * * - - - - * - - - - - - - * * | * - * * * * * * | <-- count9
LC58 -> * * - - - - * - - - - - - - * * | * - * * * * * * | <-- count8
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\test\p2s.rpt
p2s
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+----------------------------- LC29 LCD0
| +--------------------------- LC27 LCD1
| | +------------------------- LC25 LCD2
| | | +----------------------- LC24 LCD3
| | | | +--------------------- LC21 LCD4
| | | | | +------------------- LC19 LCD5
| | | | | | +----------------- LC17 LCD6
| | | | | | | +--------------- LC31 reg3
| | | | | | | | +------------- LC20 reg2
| | | | | | | | | +----------- LC28 reg1
| | | | | | | | | | +--------- LC26 reg0
| | | | | | | | | | | +------- LC18 temp
| | | | | | | | | | | | +----- LC22 i2
| | | | | | | | | | | | | +--- LC23 i1
| | | | | | | | | | | | | | +- LC30 i0
| | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'B':
LC29 -> * - - - - - - - - - - - - - - | - * - - - - - - | <-- LCD0
LC27 -> - * - - - - - - - - - - - - - | - * - - - - - - | <-- LCD1
LC25 -> - - * - - - - - - - - - - - - | - * - - - - - - | <-- LCD2
LC24 -> - - - * - - - - - - - - - - - | - * - - - - - - | <-- LCD3
LC21 -> - - - - * - - - - - - - - - - | - * - - - - - - | <-- LCD4
LC19 -> - - - - - * - - - - - - - - - | - * - - - - - - | <-- LCD5
LC17 -> - - - - - - * - - - - - - - - | - * - - - - - - | <-- LCD6
LC31 -> - - - - - - - * - - - * - - - | - * - - - - - - | <-- reg3
LC20 -> - - - - - - - - * - - * - - - | - * - - - - - - | <-- reg2
LC28 -> - - - - - - - - - * - * - - - | - * - - - - - - | <-- reg1
LC26 -> - - - - - - - - - - * * - - - | - * - - - - - - | <-- reg0
LC18 -> - * * * - - * - - - - * - - - | - * - - - - - - | <-- temp
LC22 -> - - - - - - - * * * * * * * * | - * - - - - - - | <-- i2
LC23 -> - - - - - - - * * * * * * * - | - * - - - - - - | <-- i1
LC30 -> - - - - - - - * * * * * * * * | - * - - - - - - | <-- i0
Pin
83 -> - - - - - - - - - - - - - - - | - - - - - - - - | <-- clk
45 -> * * * * * * * * * * * * * * * | - * - - - - - - | <-- enable
41 -> - - - - - - - - - - * - - - - | - * - - - - - - | <-- input0
40 -> - - - - - - - - - * - - - - - | - * - - - - - - | <-- input1
39 -> - - - - - - - - * - - - - - - | - * - - - - - - | <-- input2
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