p2s.vhd

用vhdl代码写的并行转串行的程序,波形图正确,已经在板子上运行过,良好

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_unsigned.ALL;
entity p2s is
 port(
     clk : IN STD_LOGIC;  
     enable : IN STD_LOGIC;
     input: IN STD_LOGIC_VECTOR(3 Downto 0);
     --output: OUT STD_ULOGIC;
     LCD: OUT STD_LOGIC_VECTOR(6 Downto 0) );
end p2s;
ARCHITECTURE Proc OF p2s IS
SIGNAL clk_2: bit;
signal reg: STD_LOGIC_VECTOR(3 Downto 0);
signal temp:STD_LOGIC;
BEGIN
Process1:Process(clk)
		VARIABLE count:integer;
	BEGIN
            if(clk' event and clk = '1') then
			    if(count<3) then
				count:= count+1;
				clk_2<='0';
			    else
				count:=0;
				clk_2<='1';
			    end if;
		    end if;

	 end process;
Process2:	process(clk_2,enable) 
	VARIABLE i:integer range 0 to 4;
	BEGIN
  		WAIT UNTIL( clk_2' event and clk_2 = '1' );
         if(enable='1') then
			    case i is
				  when 0 =>
					reg<=input;
                     i := 1;
				   when 1 =>
                    --output<=reg(0);
                    temp <= reg(0);
					i:=2;
				 when 2 =>
				    --output<=reg(1);
                    temp <= reg(1);
					 i:=3;
				 when 3 =>
					--output<=reg(2);
                    temp <= reg(2);
			        i:=4;
                 when 4 =>
                    --output <= reg(3);
                    temp <= reg(3);
                    i := 0;                          
            end case;
        end if;
    END process;

 Process3:  process(clk_2,enable)
              BEGIN
        WAIT UNTIL( clk_2' event and clk_2 = '1' );
        if(enable='1') then
          case temp is
           when '0' =>
           LCD <= "1111110";
           when '1' =>
           LCD <= "0110000";
           when others =>
           LCD <= "1111111";
        end case;  
 end if;
 
end process;   
end Proc;