📄 send.vhd
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LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity send is
port(CS,A0,RD,WR:in std_logic;
TXC,reset:in std_logic;
d_in:in std_logic_vector(7 downto 0);
D_OUT,TBE_out:out std_logic);
END;
architecture behavior of send is
signal clk,TBE:std_logic;
signal count1:integer range 0 to 9;
signal count2:integer range 0 to 22;
signal temp:std_logic_vector(9 downto 0);
begin
p1:process(TXC,reset)
begin
if(txc'event and txc='1')then
if(reset='1'and CS='0'AND RD='1'AND WR='0'AND A0='0')then
if(count2=22)then
count2<=0;clk<=not clk;
else
count2<=count2+1;
end if;end if;end if;
end process p1;
p2:process(clk)
begin
if(reset='0'or not(CS='0'AND RD='1'AND WR='0'AND A0='0'))then count1<=0;
else
if(clk'event and clk='1')then
if(count1=9)then count1<=0;
else count1<=count1+1;
end if;end if;end if;
end process p2;
p3:process(clk)
begin
if(reset='0'or not(CS='0'AND RD='1'AND WR='0'AND A0='0'))then temp(9)<='1';TBE<='1';
else
if(clk'event and clk='1')then
if(count1=0)then
temp(9 downto 0)<=('0'&d_in(0)&d_in(1)&d_in(2)&d_in(3)&d_in(4)&d_in(5)&d_in(6)&d_in(7)&'1');
TBE<='0';
else
if(count1=9)then TBE<='1';temp(9)<='1'; --downto 1)<=temp(8 downto 0);
else temp(9 downto 1)<=temp(8 downto 0);
end if;end if;
end if;
end if;
END PROCESS;
D_OUT<=temp(9);
TBE_out<=TBE;
end;
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