control.rpt

本程序是用VHDL语言实现异步通信控制器

count24  = TFFE( _EQ011, GLOBAL( RXC),  VCC,  VCC,  VCC);
  _EQ011 = !count20 &  count21 &  count22 & !count23 &  count24 & !CS & !RD & 
              RESET &  st &  WR
         #  count20 &  count21 &  count22 &  count23 & !CS & !RD &  RESET & 
              st &  WR;

-- Node name is ':34' = 'count30' 
-- Equation name is 'count30', location is LC053, type is buried.
count30  = TFFE( _EQ012, GLOBAL( RXC),  VCC,  VCC,  VCC);
  _EQ012 = !count30 & !CS & !RD &  RESET &  start &  WR
         #  count30 & !CS & !RD &  RESET &  WR;

-- Node name is ':33' = 'count31' 
-- Equation name is 'count31', location is LC052, type is buried.
count31  = DFFE( _EQ013 $  VCC, GLOBAL( RXC),  VCC,  VCC,  VCC);
  _EQ013 =  count30 &  count31 & !CS & !RD &  RESET &  WR
         # !count31 &  count32 &  count33 & !count34 &  count35
         # !CS & !RD &  RESET & !start &  WR
         # !count31 &  _X005;
  _X005  = EXP( count30 & !CS & !RD &  RESET &  WR);

-- Node name is ':32' = 'count32' 
-- Equation name is 'count32', location is LC051, type is buried.
count32  = TFFE( _EQ014, GLOBAL( RXC),  VCC,  VCC,  VCC);
  _EQ014 =  count30 & !count31 &  count32 &  count33 & !count34 &  count35 & 
             !CS & !RD &  RESET &  WR
         #  count30 &  count31 & !count32 & !CS & !RD &  RESET &  start &  WR
         #  count30 &  count31 &  count32 & !CS & !RD &  RESET &  WR
         #  count32 & !CS & !RD &  RESET & !start &  WR;

-- Node name is ':31' = 'count33' 
-- Equation name is 'count33', location is LC050, type is buried.
count33  = TFFE( _EQ015, GLOBAL( RXC),  VCC,  VCC,  VCC);
  _EQ015 =  count30 & !count31 &  count32 &  count33 & !count34 &  count35 & 
             !CS & !RD &  RESET &  WR &  _X006
         #  count30 &  count31 &  count32 & !count33 & !CS & !RD &  RESET & 
              start &  WR &  _X007
         #  count33 & !CS & !RD &  RESET &  WR &  _X008;
  _X006  = EXP( count30 &  count31 &  count32);
  _X007  = EXP(!count30 & !count31 & !count32 & !count34 & !count35);
  _X008  = EXP(!_LC058 &  start);

-- Node name is ':30' = 'count34' 
-- Equation name is 'count34', location is LC061, type is buried.
count34  = DFFE( _EQ016 $  VCC, GLOBAL( RXC),  VCC,  VCC,  VCC);
  _EQ016 = !count30 & !count31 & !count32 & !count33 & !count34 & !count35 & 
             !_LC062
         #  count30 & !count31 &  count32 &  count33 & !count34 &  count35
         # !CS & !_LC055 & !RD &  RESET &  WR &  _X001
         # !CS & !RD &  RESET & !start &  WR
         # !count34 &  _X009;
  _X001  = EXP(!count30 & !count31 & !count32 & !count33 & !count34 & !count35);
  _X009  = EXP(!CS & !RD &  RESET &  WR);

-- Node name is ':29' = 'count35' 
-- Equation name is 'count35', location is LC059, type is buried.
count35  = DFFE( _EQ017 $  VCC, GLOBAL( RXC),  VCC,  VCC,  VCC);
  _EQ017 =  count30 & !count31 &  count32 &  count33 & !count34 &  count35 & 
             !CS & !RD &  RESET &  WR
         # !count30 & !count31 & !count32 & !count33 & !count34 & !count35 & 
             !_LC060
         # !CS & !_LC054 & !RD &  RESET &  WR &  _X001
         # !CS & !RD &  RESET & !start &  WR
         # !count35 &  _X009;
  _X001  = EXP(!count30 & !count31 & !count32 & !count33 & !count34 & !count35);
  _X009  = EXP(!CS & !RD &  RESET &  WR);

-- Node name is ':38' = 'count40' 
-- Equation name is 'count40', location is LC037, type is buried.
count40  = TFFE(!_EQ018,  RXEN,  VCC,  VCC,  VCC);
  _EQ018 =  count40 & !count41 & !count42 &  count43 & !RXD;

-- Node name is ':37' = 'count41' 
-- Equation name is 'count41', location is LC020, type is buried.
count41  = DFFE( _EQ019 $  _LC024,  RXEN,  VCC,  VCC,  VCC);
  _EQ019 =  count40 & !count41 & !count42 &  count43 &  _LC024;

-- Node name is ':36' = 'count42' 
-- Equation name is 'count42', location is LC036, type is buried.
count42  = TFFE( _EQ020,  RXEN,  VCC,  VCC,  VCC);
  _EQ020 =  count40 &  count41;

-- Node name is ':35' = 'count43' 
-- Equation name is 'count43', location is LC035, type is buried.
count43  = DFFE( _EQ021 $  _LC022,  RXEN,  VCC,  VCC,  VCC);
  _EQ021 =  count40 & !count41 & !count42 &  count43 &  _LC022 &  RXD
         #  count40 & !count41 & !count42 &  count43 & !_LC022 & !RXD;

-- Node name is 'FE' 
-- Equation name is 'FE', location is LC056, type is output.
 FE      = LCELL( _EQ022 $  GND);
  _EQ022 =  LDRB & !RXD &  start;

-- Node name is 'LDRB' = 'stop' 
-- Equation name is 'LDRB', location is LC017, type is output.
 LDRB    = DFFE( _EQ023 $  GND, !RXEN,  VCC,  VCC,  VCC);
  _EQ023 =  count40 & !count41 & !count42 &  count43;

-- Node name is 'LDSR' 
-- Equation name is 'LDSR', location is LC064, type is output.
 LDSR    = LCELL( _EQ024 $  GND);
  _EQ024 = !start &  t;

-- Node name is 'RXEN' = 'clk1' 
-- Equation name is 'RXEN', location is LC033, type is output.
 RXEN    = TFFE( _EQ025, GLOBAL( RXC),  VCC,  VCC,  VCC);
  _EQ025 = !count20 &  count21 &  count22 & !count23 &  count24 & !CS & !RD & 
              RESET &  st &  WR;

-- Node name is 'SCLK' 
-- Equation name is 'SCLK', location is LC049, type is output.
 SCLK    = LCELL( _EQ026 $  clk2);
  _EQ026 =  clk2 &  LDRB;

-- Node name is ':15' = 'st' 
-- Equation name is 'st', location is LC048, type is buried.
st       = TFFE( _EQ027, GLOBAL( RXC),  VCC,  VCC,  VCC);
  _EQ027 = !CS & !RD &  RESET & !RXD & !st & !start &  WR;

-- Node name is ':13' = 'start' 
-- Equation name is 'start', location is LC034, type is buried.
start    = TFFE( _EQ028, GLOBAL( RXC),  VCC,  VCC,  VCC);
  _EQ028 = !count10 &  count11 &  count12 & !count13 &  count14 & !CS & !RD & 
              RESET & !RXD & !start &  WR
         # !CS &  LDRB & !RD &  RESET &  RXD &  start &  WR;

-- Node name is ':14' = 't' 
-- Equation name is 't', location is LC063, type is buried.
t        = TFFE( _EQ029, GLOBAL( RXC),  VCC,  VCC,  VCC);
  _EQ029 = !CS &  LDRB & !RD &  RESET &  RXD &  start &  t &  WR
         # !CS & !RD &  RESET & !RXD & !start & !t &  WR;

-- Node name is '|LPM_ADD_SUB:884|addcore:adder|addcore:adder0|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC062', type is buried 
_LC062   = LCELL( count34 $  _EQ030);
  _EQ030 =  count30 &  count31 &  count32 &  count33;

-- Node name is '|LPM_ADD_SUB:884|addcore:adder|addcore:adder0|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC060', type is buried 
_LC060   = LCELL( count35 $  _EQ031);
  _EQ031 =  count30 &  count31 &  count32 &  count33 &  count34;

-- Node name is '|LPM_ADD_SUB:941|addcore:adder|addcore:adder0|gcp2' from file "addcore.tdf" line 160, column 8
-- Equation name is '_LC058', type is buried 
_LC058   = LCELL( _EQ032 $  GND);
  _EQ032 =  count30 &  count31 &  count32;

-- Node name is '|LPM_ADD_SUB:941|addcore:adder|addcore:adder0|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC055', type is buried 
_LC055   = LCELL( count34 $  _EQ033);
  _EQ033 =  count30 &  count31 &  count32 &  count33;

-- Node name is '|LPM_ADD_SUB:941|addcore:adder|addcore:adder0|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC054', type is buried 
_LC054   = LCELL( count35 $  _EQ034);
  _EQ034 =  count30 &  count31 &  count32 &  count33 &  count34;

-- Node name is '|LPM_ADD_SUB:1415|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC024', type is buried 
_LC024   = LCELL( count41 $  count40);

-- Node name is '|LPM_ADD_SUB:1415|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC022', type is buried 
_LC022   = LCELL( count43 $  _EQ035);
  _EQ035 =  count40 &  count41 &  count42;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                        d:\zong\control.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 4,951K