📄 receiver.rpt
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-- Equation name is '_LC050', type is buried
_LC050 = LCELL( _LC064 $ _EQ040);
_EQ040 = _LC057 & _LC059 & _LC061 & _LC062;
-- Node name is '|control:u1|LPM_ADD_SUB:941|addcore:adder|addcore:adder0|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC053', type is buried
_LC053 = LCELL( _LC063 $ _EQ041);
_EQ041 = _LC057 & _LC059 & _LC061 & _LC062 & _LC064;
-- Node name is '|control:u1|LPM_ADD_SUB:1415|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC006', type is buried
_LC006 = LCELL( _LC004 $ _LC005);
-- Node name is '|control:u1|LPM_ADD_SUB:1415|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC007', type is buried
_LC007 = LCELL( _LC001 $ _EQ042);
_EQ042 = _LC003 & _LC004 & _LC005;
-- Node name is '|control:u1|:15' = '|control:u1|st'
-- Equation name is '_LC054', type is buried
_LC054 = TFFE( _EQ043, GLOBAL( RXC), VCC, VCC, VCC);
_EQ043 = !CS & !_LC039 & !_LC054 & !RD & RESET & !RXD & WR;
-- Node name is '|control:u1|:13' = '|control:u1|start'
-- Equation name is '_LC039', type is buried
_LC039 = TFFE( _EQ044, GLOBAL( RXC), VCC, VCC, VCC);
_EQ044 = !CS & !_LC039 & _LC044 & !_LC045 & _LC046 & _LC047 & !_LC048 &
!RD & RESET & !RXD & WR
# !CS & _LC039 & RBF & !RD & RESET & RXD & WR;
-- Node name is '|control:u1|:14' = '|control:u1|t'
-- Equation name is '_LC043', type is buried
_LC043 = TFFE( _EQ045, GLOBAL( RXC), VCC, VCC, VCC);
_EQ045 = !CS & _LC039 & _LC043 & RBF & !RD & RESET & RXD & WR
# !CS & !_LC039 & !_LC043 & !RD & RESET & !RXD & WR;
-- Node name is '|shifter:u2|:26' = '|shifter:u2|temp1'
-- Equation name is '_LC034', type is buried
_LC034 = DFFE( _EQ046 $ GND, _LC018, VCC, VCC, VCC);
_EQ046 = !_LC039 & _LC043 & !RBF
# _LC034 & RBF
# _LC035 & !RBF;
-- Node name is '|shifter:u2|:25' = '|shifter:u2|temp2'
-- Equation name is '_LC035', type is buried
_LC035 = DFFE( _EQ047 $ GND, _LC018, VCC, VCC, VCC);
_EQ047 = !_LC039 & _LC043 & !RBF
# _LC035 & RBF
# _LC036 & !RBF;
-- Node name is '|shifter:u2|:24' = '|shifter:u2|temp3'
-- Equation name is '_LC036', type is buried
_LC036 = DFFE( _EQ048 $ GND, _LC018, VCC, VCC, VCC);
_EQ048 = !_LC039 & _LC043 & !RBF
# _LC036 & RBF
# _LC037 & !RBF;
-- Node name is '|shifter:u2|:23' = '|shifter:u2|temp4'
-- Equation name is '_LC037', type is buried
_LC037 = DFFE( _EQ049 $ GND, _LC018, VCC, VCC, VCC);
_EQ049 = !_LC039 & _LC043 & !RBF
# _LC037 & RBF
# _LC040 & !RBF;
-- Node name is '|shifter:u2|:22' = '|shifter:u2|temp5'
-- Equation name is '_LC040', type is buried
_LC040 = DFFE( _EQ050 $ GND, _LC018, VCC, VCC, VCC);
_EQ050 = !_LC039 & _LC043 & !RBF
# _LC040 & RBF
# _LC042 & !RBF;
-- Node name is '|shifter:u2|:21' = '|shifter:u2|temp6'
-- Equation name is '_LC042', type is buried
_LC042 = DFFE( _EQ051 $ GND, _LC018, VCC, VCC, VCC);
_EQ051 = !_LC039 & _LC043 & !RBF
# _LC042 & RBF
# _LC038 & !RBF;
-- Node name is '|shifter:u2|:20' = '|shifter:u2|temp7'
-- Equation name is '_LC038', type is buried
_LC038 = DFFE( _EQ052 $ GND, _LC018, VCC, VCC, VCC);
_EQ052 = !_LC039 & _LC043 & !RBF
# _LC038 & RBF
# _LC033 & !RBF;
-- Node name is '|shifter:u2|:19' = '|shifter:u2|temp8'
-- Equation name is '_LC033', type is buried
_LC033 = DFFE( _EQ053 $ GND, _LC018, VCC, VCC, VCC);
_EQ053 = !_LC039 & _LC043 & !RBF
# _LC033 & RBF
# !RBF & RXD;
-- Node name is '|shifter:u2|~799~1'
-- Equation name is '_LC012', type is buried
-- synthesized logic cell
_LC012 = LCELL( _EQ054 $ GND);
_EQ054 = !A0 & TBE;
-- Node name is '|shifter:u2|~875~1'
-- Equation name is '_LC002', type is buried
-- synthesized logic cell
_LC002 = LCELL( _EQ055 $ _EQ056);
_EQ055 = !A0 & !_LC022 & !_LC026 & !_LC028 & _LC033 & _LC034 & _LC035 &
_LC036 & _LC037 & _LC038 & TBE & _X017 & _X018 & _X019 &
_X020 & _X021 & _X022 & _X023 & _X024 & _X025 & _X026 &
_X027 & _X028 & _X029
# !A0 & !_LC022 & !_LC026 & !_LC028 & !_LC033 & _LC034 & _LC035 &
_LC036 & _LC037 & !_LC038 & TBE & _X017 & _X018 & _X019 &
_X020 & _X021 & _X022 & _X023 & _X024 & _X025 & _X026 &
_X027 & _X028 & _X029
# !A0 & !_LC022 & !_LC026 & !_LC028 & _LC033 & !_LC034 & _LC035 &
_LC036 & _LC037 & !_LC038 & TBE & _X017 & _X018 & _X019 &
_X020 & _X021 & _X022 & _X023 & _X024 & _X025 & _X026 &
_X027 & _X028 & _X029
# !A0 & !_LC022 & !_LC026 & !_LC028 & _LC033 & _LC034 & !_LC035 &
_LC036 & _LC037 & !_LC038 & TBE & _X017 & _X018 & _X019 &
_X020 & _X021 & _X022 & _X023 & _X024 & _X025 & _X026 &
_X027 & _X028 & _X029;
_X017 = EXP(!_LC033 & !_LC034 & !_LC035 & _LC036 & !_LC037 & _LC038);
_X018 = EXP( _LC033 & !_LC034 & !_LC035 & !_LC036 & _LC037 & !_LC038);
_X019 = EXP(!_LC033 & !_LC034 & _LC035 & _LC036 & !_LC037 & !_LC038);
_X020 = EXP(!_LC033 & _LC034 & !_LC035 & _LC036 & !_LC037 & !_LC038);
_X021 = EXP(!_LC033 & !_LC034 & !_LC035 & !_LC036 & !_LC037 & !_LC038);
_X022 = EXP( _LC033 & !_LC034 & !_LC035 & !_LC036 & !_LC037 & _LC038);
_X023 = EXP(!_LC033 & _LC034 & !_LC035 & !_LC036 & !_LC037 & _LC038);
_X024 = EXP(!_LC033 & !_LC034 & _LC035 & !_LC036 & !_LC037 & _LC038);
_X025 = EXP( _LC033 & !_LC034 & !_LC035 & _LC036 & !_LC037 & !_LC038);
_X026 = EXP(!_LC033 & !_LC034 & !_LC035 & !_LC036 & _LC037 & _LC038);
_X027 = EXP( _LC033 & _LC034 & !_LC035 & !_LC036 & !_LC037 & !_LC038);
_X028 = EXP( _LC033 & !_LC034 & _LC035 & !_LC036 & !_LC037 & !_LC038);
_X029 = EXP(!_LC033 & _LC034 & _LC035 & !_LC036 & !_LC037 & !_LC038);
_EQ056 = !A0 & !_LC022 & !_LC026 & !_LC028 & TBE & _X017 & _X018 &
_X019 & _X020 & _X021 & _X022 & _X023 & _X024 & _X025 &
_X026 & _X027 & _X028 & _X029;
_X017 = EXP(!_LC033 & !_LC034 & !_LC035 & _LC036 & !_LC037 & _LC038);
_X018 = EXP( _LC033 & !_LC034 & !_LC035 & !_LC036 & _LC037 & !_LC038);
_X019 = EXP(!_LC033 & !_LC034 & _LC035 & _LC036 & !_LC037 & !_LC038);
_X020 = EXP(!_LC033 & _LC034 & !_LC035 & _LC036 & !_LC037 & !_LC038);
_X021 = EXP(!_LC033 & !_LC034 & !_LC035 & !_LC036 & !_LC037 & !_LC038);
_X022 = EXP( _LC033 & !_LC034 & !_LC035 & !_LC036 & !_LC037 & _LC038);
_X023 = EXP(!_LC033 & _LC034 & !_LC035 & !_LC036 & !_LC037 & _LC038);
_X024 = EXP(!_LC033 & !_LC034 & _LC035 & !_LC036 & !_LC037 & _LC038);
_X025 = EXP( _LC033 & !_LC034 & !_LC035 & _LC036 & !_LC037 & !_LC038);
_X026 = EXP(!_LC033 & !_LC034 & !_LC035 & !_LC036 & _LC037 & _LC038);
_X027 = EXP( _LC033 & _LC034 & !_LC035 & !_LC036 & !_LC037 & !_LC038);
_X028 = EXP( _LC033 & !_LC034 & _LC035 & !_LC036 & !_LC037 & !_LC038);
_X029 = EXP(!_LC033 & _LC034 & _LC035 & !_LC036 & !_LC037 & !_LC038);
-- Node name is '|shifter:u2|~875~2'
-- Equation name is '_LC022', type is buried
-- synthesized logic cell
_LC022 = LCELL( _EQ057 $ GND);
_EQ057 = !_LC033 & !_LC034 & _LC035 & _LC036 & _LC037 & _LC038
# !_LC033 & _LC034 & !_LC035 & _LC036 & _LC037 & _LC038
# _LC033 & !_LC034 & !_LC035 & _LC036 & _LC037 & _LC038
# _LC033 & _LC034 & _LC035 & !_LC036 & _LC037 & !_LC038
# !_LC033 & _LC034 & _LC035 & !_LC036 & _LC037 & _LC038;
-- Node name is '|shifter:u2|~875~3'
-- Equation name is '_LC028', type is buried
-- synthesized logic cell
_LC028 = LCELL( _EQ058 $ GND);
_EQ058 = _LC033 & !_LC034 & _LC035 & !_LC036 & _LC037 & _LC038
# _LC033 & _LC034 & !_LC035 & !_LC036 & _LC037 & _LC038
# _LC033 & _LC034 & _LC035 & _LC036 & !_LC037 & !_LC038
# !_LC033 & _LC034 & _LC035 & _LC036 & !_LC037 & _LC038
# _LC033 & !_LC034 & _LC035 & _LC036 & !_LC037 & _LC038;
-- Node name is '|shifter:u2|~875~4'
-- Equation name is '_LC026', type is buried
-- synthesized logic cell
_LC026 = LCELL( _EQ059 $ GND);
_EQ059 = _LC033 & _LC034 & !_LC035 & _LC036 & !_LC037 & _LC038
# _LC033 & _LC034 & _LC035 & !_LC036 & !_LC037 & _LC038
# !_LC033 & !_LC034 & !_LC035 & _LC036 & _LC037 & !_LC038
# !_LC033 & !_LC034 & _LC035 & !_LC036 & _LC037 & !_LC038
# !_LC033 & _LC034 & !_LC035 & !_LC036 & _LC037 & !_LC038;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\zong\receiver.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 5,495K
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