📄 hao1.rpt
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hao1
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
17 (25) (B) INPUT 0 0 0 0 0 10 32 A0
4 (16) (A) INPUT 0 0 0 0 0 9 52 CS
67 104 G BIDIR 0 0 0 4 2 0 2 D0
65 101 G BIDIR 0 0 0 4 3 0 2 D1
64 99 G BIDIR 0 0 0 4 2 0 1 D2
76 120 H BIDIR 0 0 0 4 3 0 1 D3
63 97 G BIDIR 0 0 0 5 3 0 1 D4
80 126 H BIDIR 0 0 0 4 2 0 1 D5
75 118 H BIDIR 0 0 0 4 2 0 1 D6
74 117 H BIDIR 0 0 0 4 2 0 1 D7
18 (24) (B) INPUT 0 0 0 0 0 9 52 RD
6 (13) (A) INPUT 0 0 0 0 0 1 37 reset
83 - - INPUT G 0 0 0 0 0 0 0 RXC
29 (38) (C) INPUT 0 0 0 0 0 1 11 RXD
2 - - INPUT G 0 0 0 0 0 0 0 TXC
11 (5) (A) INPUT 0 0 0 0 0 9 52 WR
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\zong\hao1.rpt
hao1
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
67 104 G TRI t 0 0 0 4 2 0 2 D0
65 101 G TRI t 0 0 0 4 3 0 2 D1
64 99 G TRI t 0 0 0 4 2 0 1 D2
76 120 H TRI t 0 0 0 4 3 0 1 D3
63 97 G TRI t 0 0 0 5 3 0 1 D4
80 126 H TRI t 0 0 0 4 2 0 1 D5
75 118 H TRI t 0 0 0 4 2 0 1 D6
74 117 H TRI t 0 0 0 4 2 0 1 D7
73 115 H OUTPUT t 0 0 0 1 7 0 0 IRQ
55 85 F FF t 2 1 1 5 6 0 0 TXD (|send:u2|:27)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\zong\hao1.rpt
hao1
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(54) 83 F SOFT s t 0 0 0 3 0 0 0 D7~1
(39) 53 D SOFT t 0 0 0 0 2 0 1 |receiver:u4|control:u1|LPM_ADD_SUB:1415|addcore:adder|addcore:adder0|result_node1
- 55 D SOFT t 0 0 0 0 4 0 1 |receiver:u4|control:u1|LPM_ADD_SUB:1415|addcore:adder|addcore:adder0|result_node3
- 102 G TFFE + t 0 0 0 5 7 1 16 |receiver:u4|control:u1|start (|receiver:u4|control:u1|:13)
- 100 G TFFE + t 0 0 0 5 3 0 9 |receiver:u4|control:u1|t (|receiver:u4|control:u1|:14)
- 98 G TFFE + t 0 0 0 5 2 0 7 |receiver:u4|control:u1|st (|receiver:u4|control:u1|:15)
(70) 109 G TFFE + t 1 0 0 5 7 0 4 |receiver:u4|control:u1|count14 (|receiver:u4|control:u1|:16)
- 110 G TFFE + t 1 0 0 5 7 0 4 |receiver:u4|control:u1|count13 (|receiver:u4|control:u1|:17)
- 111 G TFFE + t 0 0 0 5 5 0 5 |receiver:u4|control:u1|count12 (|receiver:u4|control:u1|:18)
- 106 G TFFE + t 0 0 0 5 4 0 6 |receiver:u4|control:u1|count11 (|receiver:u4|control:u1|:19)
(69) 107 G TFFE + t 1 0 0 5 7 0 6 |receiver:u4|control:u1|count10 (|receiver:u4|control:u1|:20)
(41) 49 D DFFE t 0 0 0 0 5 9 16 |receiver:u4|control:u1|stop (|receiver:u4|control:u1|:21)
- 68 E TFFE + t 0 0 0 4 6 0 5 |receiver:u4|control:u1|count24 (|receiver:u4|control:u1|:22)
(46) 69 E TFFE + t 0 0 0 4 4 0 5 |receiver:u4|control:u1|count23 (|receiver:u4|control:u1|:23)
- 70 E TFFE + t 0 0 0 4 6 0 6 |receiver:u4|control:u1|count22 (|receiver:u4|control:u1|:24)
- 71 E TFFE + t 0 0 0 4 6 0 6 |receiver:u4|control:u1|count21 (|receiver:u4|control:u1|:25)
(49) 73 E TFFE + t 1 0 1 4 6 0 6 |receiver:u4|control:u1|count20 (|receiver:u4|control:u1|:26)
(44) 65 E TFFE + t 0 0 0 4 6 0 13 |receiver:u4|control:u1|clk1 (|receiver:u4|control:u1|:27)
- 62 D DFFE t 0 0 0 1 6 0 5 |receiver:u4|control:u1|count43 (|receiver:u4|control:u1|:35)
(33) 64 D TFFE t 0 0 0 0 3 0 5 |receiver:u4|control:u1|count42 (|receiver:u4|control:u1|:36)
- 52 D DFFE t 0 0 0 0 6 0 7 |receiver:u4|control:u1|count41 (|receiver:u4|control:u1|:37)
- 50 D TFFE t 0 0 0 1 5 0 7 |receiver:u4|control:u1|count40 (|receiver:u4|control:u1|:38)
(79) 125 H DFFE t 0 0 0 1 1 2 0 |receiver:u4|shifter:u2|:17
- 122 H DFFE t 0 0 0 1 5 1 5 |receiver:u4|shifter:u2|temp8 (|receiver:u4|shifter:u2|:19)
- 119 H DFFE t 0 0 0 0 6 1 7 |receiver:u4|shifter:u2|temp7 (|receiver:u4|shifter:u2|:20)
- 124 H DFFE t 0 0 0 0 6 1 6 |receiver:u4|shifter:u2|temp6 (|receiver:u4|shifter:u2|:21)
- 113 H DFFE t 0 0 0 0 6 1 3 |receiver:u4|shifter:u2|temp5 (|receiver:u4|shifter:u2|:22)
- 121 H DFFE t 0 0 0 0 6 1 3 |receiver:u4|shifter:u2|temp4 (|receiver:u4|shifter:u2|:23)
- 103 G DFFE t 0 0 0 0 6 1 3 |receiver:u4|shifter:u2|temp3 (|receiver:u4|shifter:u2|:24)
- 108 G DFFE t 0 0 0 0 6 1 3 |receiver:u4|shifter:u2|temp2 (|receiver:u4|shifter:u2|:25)
(71) 112 G DFFE t 0 0 0 0 6 1 2 |receiver:u4|shifter:u2|temp1 (|receiver:u4|shifter:u2|:26)
- 87 F SOFT s t 0 0 0 1 1 0 1 |receiver:u4|shifter:u2|~658~1
- 92 F SOFT s t 0 0 0 1 1 0 4 |receiver:u4|shifter:u2|~659~1
- 114 H SOFT s t 0 0 0 1 2 0 3 |receiver:u4|shifter:u2|~667~1
(68) 105 G SOFT s t 13 0 1 1 6 0 4 |receiver:u4|shifter:u2|~733~1
- 116 H SOFT s t 12 0 0 1 9 1 0 |receiver:u4|shifter:u2|~738~1
(77) 123 H SOFT s t 1 0 1 1 7 0 1 |receiver:u4|shifter:u2|~738~2
(81) 128 H SOFT s t 1 0 1 1 7 0 1 |receiver:u4|shifter:u2|~738~3
- 127 H SOFT s t 1 0 1 1 7 0 1 |receiver:u4|shifter:u2|~738~4
(52) 80 E DFFE t 3 1 0 5 3 1 0 |reg:u3|ERXE (|reg:u3|:28)
(62) 96 F DFFE t 3 1 0 5 6 1 0 |reg:u3|ETBE (|reg:u3|:29)
- 95 F DFFE t 3 1 0 5 6 1 0 |reg:u3|ERBF (|reg:u3|:30)
- 78 E SOFT s t 0 0 0 3 0 0 2 |selection:u1|~301~1
(48) 72 E SOFT s t 0 0 0 3 0 0 2 |selection:u1|~306~1
(17) 25 B LCELL s t 2 2 0 3 2 0 2 |selection:u1|~308~1
- 58 D LCELL s t 2 2 0 3 2 0 2 |selection:u1|~317~1
(35) 59 D LCELL s t 2 2 0 3 2 0 2 |selection:u1|~326~1
(16) 27 B LCELL s t 2 2 0 3 2 0 2 |selection:u1|~335~1
- 30 B LCELL s t 2 2 0 3 2 0 2 |selection:u1|~344~1
- 79 E SOFT s t 0 0 0 3 3 0 2 |selection:u1|~350~1
- 76 E LCELL s t 0 0 0 3 2 0 4 |selection:u1|~354~1
(50) 75 E LCELL s t 1 1 0 3 1 0 4 |selection:u1|~355~1
- 90 F SOFT s t 0 0 0 0 2 0 1 |selection:u1|~356~1
- 89 F LCELL s t 0 0 0 3 2 0 5 |selection:u1|~363~1
(57) 88 F LCELL s t 3 3 0 3 3 0 5 |selection:u1|~364~1
(61) 94 F SOFT s t 0 0 0 0 2 0 1 |selection:u1|~365~1
(56) 86 F LCELL s t 0 0 0 3 2 0 5 |selection:u1|~372~1
(58) 91 F LCELL s t 3 3 0 3 3 0 5 |selection:u1|~373~1
(51) 77 E SOFT t 0 0 0 0 2 0 1 |send:u2|LPM_ADD_SUB:381|addcore:adder|addcore:adder0|result_node1
(60) 93 F SOFT t 0 0 0 0 4 0 1 |send:u2|LPM_ADD_SUB:381|addcore:adder|addcore:adder0|result_node3
- 63 D TFFE + t 0 0 0 5 5 0 5 |send:u2|count24 (|send:u2|:17)
(34) 61 D TFFE + t 0 0 0 5 3 0 5 |send:u2|count23 (|send:u2|:18)
- 60 D TFFE + t 0 0 0 5 5 0 6 |send:u2|count22 (|send:u2|:19)
- 54 D TFFE + t 0 0 0 5 5 0 6 |send:u2|count21 (|send:u2|:20)
(40) 51 D TFFE + t 1 0 1 5 5 0 6 |send:u2|count20 (|send:u2|:21)
(37) 56 D TFFE + t 0 0 0 5 5 1 14 |send:u2|clk (|send:u2|:22)
- 41 C DFFE t 1 1 0 5 6 1 18 |send:u2|count13 (|send:u2|:23)
- 82 F TFFE t 1 1 0 5 3 1 18 |send:u2|count12 (|send:u2|:24)
- 44 C DFFE t 1 1 0 5 6 1 20 |send:u2|count11 (|send:u2|:25)
- 81 F TFFE t 1 1 0 5 1 1 20 |send:u2|count10 (|send:u2|:26)
(36) 57 D DFFE t 10 0 1 5 9 1 1 |send:u2|temp8 (|send:u2|:28)
- 33 C DFFE t 10 0 1 5 9 0 2 |send:u2|temp7 (|send:u2|:29)
- 66 E DFFE t 10 0 1 5 9 0 2 |send:u2|temp6 (|send:u2|:30)
- 34 C DFFE t 2 2 0 5 8 0 3 |send:u2|temp5 (|send:u2|:31)
- 39 C TFFE t 2 1 1 5 8 0 3 |send:u2|temp4 (|send:u2|:32)
(30) 37 C TFFE t 2 1 1 5 8 0 3 |send:u2|temp3 (|send:u2|:33)
- 47 C TFFE t 2 1 1 5 8 0 3 |send:u2|temp2 (|send:u2|:34)
(31) 35 C TFFE t 2 1 1 5 8 0 3 |send:u2|temp1 (|send:u2|:35)
- 74 E TFFE t 0 0 0 5 6 0 2 |send:u2|temp0 (|send:u2|:36)
- 84 F TFFE t 1 1 0 5 6 2 9 |send:u2|TBE (|send:u2|:37)
(24) 46 C SOFT s t 0 0 0 0 6 0 1 |send:u2|~1218~1
(25) 45 C SOFT s t 0 0 0 0 6 0 1 |send:u2|~1224~1
(29) 38 C SOFT s t 0 0 0 0 6 0 1 |send:u2|~1230~1
- 36 C SOFT s t 0 0 0 0 6 0 1 |send:u2|~1236~1
(45) 67 E SOFT s t 0 0 0 0 6 0 1 |send:u2|~1242~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\zong\hao1.rpt
hao1
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+----- LC25 |selection:u1|~308~1
| +--- LC27 |selection:u1|~335~1
| | +- LC30 |selection:u1|~344~1
| | |
| | | Other LABs fed by signals
| | | that feed LAB 'B'
LC | | | | A B C D E F G H | Logic cells that feed LAB 'B':
LC25 -> * - - | - * * - - - - - | <-- |selection:u1|~308~1
LC27 -> - * - | - * * - - - - - | <-- |selection:u1|~335~1
LC30 -> - - * | - * * - - - - - | <-- |selection:u1|~344~1
Pin
4 -> * * * | - * * * * * * * | <-- CS
18 -> * * * | - * * * * * * * | <-- RD
83 -> - - - | - - - - - - - - | <-- RXC
2 -> - - - | - - - - - - - - | <-- TXC
11 -> * * * | - * * * * * * * | <-- WR
LC120-> - - * | - * - - - - - - | <-- D3
LC97 -> - * - | - * - - - - - - | <-- D4
LC117-> * - - | - * - - - - - - | <-- D7
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\zong\hao1.rpt
hao1
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+----------------------- LC41 |send:u2|count13
| +--------------------- LC44 |send:u2|count11
| | +------------------- LC33 |send:u2|temp7
| | | +----------------- LC34 |send:u2|temp5
| | | | +--------------- LC39 |send:u2|temp4
| | | | | +------------- LC37 |send:u2|temp3
| | | | | | +----------- LC47 |send:u2|temp2
| | | | | | | +--------- LC35 |send:u2|temp1
| | | | | | | | +------- LC46 |send:u2|~1218~1
| | | | | | | | | +----- LC45 |send:u2|~1224~1
| | | | | | | | | | +--- LC38 |send:u2|~1230~1
| | | | | | | | | | | +- LC36 |send:u2|~1236~1
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