eve.rpt

本程序是用VHDL语言实现异步通信控制器

  _EQ025 = !A0 & !count10 & !count11 & !count12 & !count13 & !CS & !D1 & 
             !_LC050 & !RD &  reset &  WR &  _X002 &  _X003 &  _X004 &  _X005
         # !A0 & !count10 &  count13 & !CS & !_LC050 & !RD &  reset & !temp5 & 
              WR &  _X002 &  _X003 &  _X004 &  _X005
         # !A0 &  count10 & !count13 & !CS & !_LC050 & !RD &  reset & !temp5 & 
              WR &  _X002 &  _X003 &  _X004 &  _X005;
  _X002  = EXP( A0 & !temp6);
  _X003  = EXP( CS & !temp6);
  _X004  = EXP(!temp6 & !WR);
  _X005  = EXP(!reset & !temp6);
  _EQ026 = !_LC050 &  _X002 &  _X003 &  _X004 &  _X005;
  _X002  = EXP( A0 & !temp6);
  _X003  = EXP( CS & !temp6);
  _X004  = EXP(!temp6 & !WR);
  _X005  = EXP(!reset & !temp6);

-- Node name is ':29' = 'temp7' 
-- Equation name is 'temp7', location is LC049, type is buried.
temp7    = DFFE( _EQ027 $  _EQ028,  clk,  VCC,  VCC,  VCC);
  _EQ027 = !A0 & !count10 & !count11 & !count12 & !count13 & !CS & !D2 & 
             !_LC062 & !RD &  reset &  WR &  _X006 &  _X007 &  _X008 &  _X009
         # !A0 & !count10 &  count13 & !CS & !_LC062 & !RD &  reset & !temp6 & 
              WR &  _X006 &  _X007 &  _X008 &  _X009
         # !A0 &  count10 & !count13 & !CS & !_LC062 & !RD &  reset & !temp6 & 
              WR &  _X006 &  _X007 &  _X008 &  _X009;
  _X006  = EXP( A0 & !temp7);
  _X007  = EXP( CS & !temp7);
  _X008  = EXP(!temp7 & !WR);
  _X009  = EXP(!reset & !temp7);
  _EQ028 = !_LC062 &  _X006 &  _X007 &  _X008 &  _X009;
  _X006  = EXP( A0 & !temp7);
  _X007  = EXP( CS & !temp7);
  _X008  = EXP(!temp7 & !WR);
  _X009  = EXP(!reset & !temp7);

-- Node name is ':28' = 'temp8' 
-- Equation name is 'temp8', location is LC046, type is buried.
temp8    = DFFE( _EQ029 $  _EQ030,  clk,  VCC,  VCC,  VCC);
  _EQ029 = !A0 & !count10 & !count11 & !count12 & !count13 & !CS & !D3 & 
             !_LC038 & !RD &  reset &  WR &  _X010 &  _X011 &  _X012 &  _X013
         # !A0 & !count10 &  count13 & !CS & !_LC038 & !RD &  reset & !temp7 & 
              WR &  _X010 &  _X011 &  _X012 &  _X013
         # !A0 &  count10 & !count13 & !CS & !_LC038 & !RD &  reset & !temp7 & 
              WR &  _X010 &  _X011 &  _X012 &  _X013;
  _X010  = EXP( A0 & !temp8);
  _X011  = EXP( CS & !temp8);
  _X012  = EXP(!temp8 & !WR);
  _X013  = EXP(!reset & !temp8);
  _EQ030 = !_LC038 &  _X010 &  _X011 &  _X012 &  _X013;
  _X010  = EXP( A0 & !temp8);
  _X011  = EXP( CS & !temp8);
  _X012  = EXP(!temp8 & !WR);
  _X013  = EXP(!reset & !temp8);

-- Node name is 'TXD' = 'temp9' 
-- Equation name is 'TXD', location is LC041, type is output.
 TXD     = DFFE( _EQ031 $  temp8,  clk,  VCC, !_EQ032,  VCC);
  _EQ031 =  count10 & !count11 & !count12 &  count13 & !temp8
         # !count10 & !count11 & !count12 & !count13 &  temp8;
  _EQ032 =  _X001;
  _X001  = EXP(!A0 & !CS & !RD &  reset &  WR);

-- Node name is '|LPM_ADD_SUB:344|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC054', type is buried 
_LC054   = LCELL( count11 $  count10);

-- Node name is '|LPM_ADD_SUB:344|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC058', type is buried 
_LC058   = LCELL( count13 $  _EQ033);
  _EQ033 =  count10 &  count11 &  count12;

-- Node name is '~990~1' 
-- Equation name is '~990~1', location is LC038, type is buried.
-- synthesized logic cell 
_LC038   = LCELL( _EQ034 $  GND);
  _EQ034 =  count10 & !count11 & !count12 &  count13 & !temp8
         # !A0 &  count12 & !CS & !RD &  reset & !temp7 &  WR
         # !A0 &  count11 & !CS & !RD &  reset & !temp7 &  WR
         #  count13 & !temp7 & !temp8
         #  RD & !temp8;

-- Node name is '~996~1' 
-- Equation name is '~996~1', location is LC062, type is buried.
-- synthesized logic cell 
_LC062   = LCELL( _EQ035 $  GND);
  _EQ035 = !A0 &  count12 & !CS & !RD &  reset & !temp6 &  WR
         # !A0 &  count11 & !CS & !RD &  reset & !temp6 &  WR
         #  count10 & !count11 & !count12 &  count13 & !temp7
         #  count13 & !temp6 & !temp7
         #  RD & !temp7;

-- Node name is '~1002~1' 
-- Equation name is '~1002~1', location is LC050, type is buried.
-- synthesized logic cell 
_LC050   = LCELL( _EQ036 $  GND);
  _EQ036 = !A0 &  count12 & !CS & !RD &  reset & !temp5 &  WR
         # !A0 &  count11 & !CS & !RD &  reset & !temp5 &  WR
         #  count10 & !count11 & !count12 &  count13 & !temp6
         #  count13 & !temp5 & !temp6
         #  RD & !temp6;

-- Node name is '~1008~1' 
-- Equation name is '~1008~1', location is LC051, type is buried.
-- synthesized logic cell 
_LC051   = LCELL( _EQ037 $  GND);
  _EQ037 = !A0 &  count12 & !CS & !RD &  reset & !temp4 &  WR
         # !A0 &  count11 & !CS & !RD &  reset & !temp4 &  WR
         #  count10 & !count11 & !count12 &  count13 & !temp5
         #  count13 & !temp4 & !temp5
         #  RD & !temp5;

-- Node name is '~1008~2' 
-- Equation name is '~1008~2', location is LC053, type is buried.
-- synthesized logic cell 
_LC053   = LCELL( _EQ038 $  GND);
  _EQ038 =  A0 & !temp5
         #  CS & !temp5
         # !temp5 & !WR
         # !reset & !temp5;

-- Node name is '~1014~1' 
-- Equation name is '~1014~1', location is LC055, type is buried.
-- synthesized logic cell 
_LC055   = LCELL( _EQ039 $  GND);
  _EQ039 = !A0 &  count12 & !CS & !RD &  reset & !temp3 &  WR
         # !A0 &  count11 & !CS & !RD &  reset & !temp3 &  WR
         #  count10 & !count11 & !count12 &  count13 & !temp4
         #  count13 & !temp3 & !temp4
         #  RD & !temp4;

-- Node name is '~1014~2' 
-- Equation name is '~1014~2', location is LC056, type is buried.
-- synthesized logic cell 
_LC056   = LCELL( _EQ040 $  GND);
  _EQ040 =  A0 & !temp4
         #  CS & !temp4
         # !temp4 & !WR
         # !reset & !temp4;

-- Node name is '~1020~1' 
-- Equation name is '~1020~1', location is LC039, type is buried.
-- synthesized logic cell 
_LC039   = LCELL( _EQ041 $  GND);
  _EQ041 = !A0 &  count12 & !CS & !RD &  reset & !temp2 &  WR
         # !A0 &  count11 & !CS & !RD &  reset & !temp2 &  WR
         #  count10 & !count11 & !count12 &  count13 & !temp3
         #  count13 & !temp2 & !temp3
         #  RD & !temp3;

-- Node name is '~1020~2' 
-- Equation name is '~1020~2', location is LC057, type is buried.
-- synthesized logic cell 
_LC057   = LCELL( _EQ042 $  GND);
  _EQ042 =  A0 & !temp3
         #  CS & !temp3
         # !temp3 & !WR
         # !reset & !temp3;

-- Node name is '~1026~1' 
-- Equation name is '~1026~1', location is LC040, type is buried.
-- synthesized logic cell 
_LC040   = LCELL( _EQ043 $  GND);
  _EQ043 = !A0 &  count12 & !CS & !RD &  reset & !temp1 &  WR
         # !A0 &  count11 & !CS & !RD &  reset & !temp1 &  WR
         #  count10 & !count11 & !count12 &  count13 & !temp2
         #  count13 & !temp1 & !temp2
         #  RD & !temp2;

-- Node name is '~1026~2' 
-- Equation name is '~1026~2', location is LC042, type is buried.
-- synthesized logic cell 
_LC042   = LCELL( _EQ044 $  GND);
  _EQ044 =  A0 & !temp2
         #  CS & !temp2
         # !temp2 & !WR
         # !reset & !temp2;

-- Node name is '~1032~1' 
-- Equation name is '~1032~1', location is LC043, type is buried.
-- synthesized logic cell 
_LC043   = LCELL( _EQ045 $  GND);
  _EQ045 = !A0 &  count12 & !CS & !RD &  reset & !temp0 &  WR
         # !A0 &  count11 & !CS & !RD &  reset & !temp0 &  WR
         #  count10 & !count11 & !count12 &  count13 & !temp1
         #  count13 & !temp0 & !temp1
         #  RD & !temp1;

-- Node name is '~1032~2' 
-- Equation name is '~1032~2', location is LC048, type is buried.
-- synthesized logic cell 
_LC048   = LCELL( _EQ046 $  GND);
  _EQ046 =  A0 & !temp1
         #  CS & !temp1
         # !temp1 & !WR
         # !reset & !temp1;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information     c:\documents and settings\focuson\desktop\zong\eve.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 7,744K