control.vhd

本程序是用VHDL语言实现异步通信控制器

LIBRARY ieee; 
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity control is
	port(CS,A0,RD,WR:in std_logic;
		 RXC,RXD,RESET:IN STD_LOGIC;
		 LDSR,LDRB,RXEN,SCLK,FE:OUT STD_LOGIC);
end;
architecture behave of control is
signal stop,cp,ctr,start,st:std_logic;
signal clk1,clk2,t:std_logic;
signal count1,count2:integer range 0 to 22;
signal count3:integer range 0 to 45;
signal count4:integer range 0 to 9 :=0;
begin
p1:process(RXC,RXD,start)
  begin
	if(RXC'event and RXC='1')then
		if(reset='1'AND CS='0'AND RD='0'AND WR='1')then
			if(start='0')then
				if(RXD='0')then
					t<='1';st<='1';
					if(count1=22)then start<='1';
					else count1<=count1+1;
				end if;end if;
			else
				if(stop='1')then
					if(RXD='1')then start<='0';count1<=0;t<='0';
					end if;
	end if;end if;end if;end if;
end process p1;
p2:process(start,RXC,RXD,stop)
  begin
  if(RXC'event and RXC='1')then
	if(reset='1'AND CS='0'AND RD='0'AND WR='1')then
		if(st='1')then
			if(count2=22)then 
				clk1<=not clk1;count2<=0;	
			else	 count2<=count2+1;end if;	
		end if;
		if(start='1')then
			if(stop='1')then	clk2<='0';end if;
			if(count3=0)then
				clk2<=not clk2;
				count3<=count3+1;
			elsif(count3=45)then count3<=0;
			else count3<=count3+1;end if;		
		else	count3<=0;
	end if;end if;end if;
  end process p2;
p3:process(clk1)
  begin
	if(clk1'event and clk1='1')then
		if(count4=9)then
			if(RXD='0')then count4<=9;
			else count4<=0;end if;
		else
			count4<=count4+1;
		end if;end if;--end if;
end process p3; 
p4:process(clk1)
  begin
	if(clk1'event and clk1='0')then
		if(count4=9)then ctr<='1';stop<='1';
		else ctr<='0';stop<='0';end if;
	end if;
  end process p4;
LDRB<=stop;--'1' when count4=10 else '0';
RXEN<=clk1;--when  cp='0' else '0';
SCLK<='0' when stop='1' else clk2;-- when  cp='0' else '0';
LDSR<='1' when t='1' and start='0' else '0';
FE<='1' when stop='1'and RXD='0' and start='1' else '0';
end;