communication.vhd

本程序是用VHDL语言实现异步通信控制器

LIBRARY ieee; 
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity communication is
	port(reset,TXC,RXC,RXD:IN STD_LOGIC;
			CS,A0,RD,WR:IN STD_LOGIC;
			TXD:OUT STD_LOGIC;
			D:INOUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END;
ARCHITECTURE behavior of communication is
signal FE,PE,OVERFLOW,RBF,TBE:STD_LOGIC;
signal	ERXE,ETBE,ERBF:STD_LOGIC;
signal LDRB,RXEN,W_r,LDSR,SCLK,Td:STD_LOGIC;
--signal RX_buf:STD_LOGIC_VECTOR(7 DOWNTO 0) :="00000000";
signal data:STD_LOGIC_VECTOR(7 DOWNTO 0);

COMPONENT send
	port(TXC,reset,W_r:in std_logic;
		 d_in:in std_logic_vector(7 downto 0);
		 D_OUT,TBE_out:out std_logic);
END COMPONENT;
COMPONENT receiver
	port(RXC,RXD,RESET,TBE,W_r:in std_logic;
		 SCLK,FE,PE:out std_logic;
		 data:out std_logic_vector(7 downto 0));
end COMPONENT;
begin
p1:process(reset,CS,A0,RD,WR)
  begin	
	if(reset='0')then
		--FE<='0';OVERFLOW<='0';PE<='0';RBF<='0';TBE<='1';
		--W_r<='0';D<="ZZZZZZZZ";RX_buf<=D;
	else
		if(CS='1')THEN	W_r<='0';--D<="ZZZZZZZZ";
		elsif(cs='0'and A0='0'and RD='0'and WR='1')then
			W_r<='0';
			--FE<='0';OVERFLOW<='0';PE<='0';
		elsif(cs='0'and A0='0'and RD='1'and WR='0')then
			W_r<='1';
		elsif(cs='0'and A0='1'and RD='0'and WR='1')then
			W_r<='0';
			--data<="000"&FE&OVERFLOW&PE&TBE&RBF;
			--FE<='0';OVERFLOW<='0';PE<='0';
		elsif(cs='0'and A0='1'and RD='1'and WR='0')then
			w_r<='1';		
			--ERXE<=RX_buf(2);ETBE<=RX_buf(1);ERBF<=RX_buf(0);D<="00000"&ERXE&ETBE&ERBF;
		--else w_r<='0';D<="ZZZZZZZZ";
		end if;
	end if;
end process p1;
PROCESS
		u1:send PORT MAP(TXC,reset,W_r,D,TXD,TBE);
		 u2:receiver PORT MAP(RXC,RXD,RESET,TBE,W_r,SCLK,FE,PE,D);end process;

end;