📄 selection.rpt
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LC57 -> - - - - - - * - - * - - - - - - | - - - * | <-- Tx_buf6
LC56 -> - - - - - - - * * - - - - - - - | - - - * | <-- Tx_buf7
LC54 -> - - - - - - - * - - - - - - - - | - - - * | <-- ~308~1~2
LC53 -> - - - - - - * - - - - - - - - - | - - - * | <-- ~317~1~2
LC52 -> - - - - - * - - - - - - - - - - | - - - * | <-- ~326~1~2
LC50 -> - - - - * - - - - - - - - - - - | - - - * | <-- ~335~1~2
LC55 -> - - - * - - - - - - - - - - - - | - - - * | <-- ~344~1~2
LC59 -> - - * - - - - - - - - - - - - - | - - - * | <-- ~353~1~2
LC63 -> - * - - - - - - - - - - - - - - | - - - * | <-- ~362~1~2
LC58 -> * - - - - - - - - - - - - - - - | - - - * | <-- ~371~1~2
Pin
9 -> * * * * * * * * * * * * * * * * | - - * * | <-- CS
68 -> - - - - - - - - - - - - - - - - | - - - - | <-- ~PIN001
12 -> * * * * * * * * * * * * * * * * | - - * * | <-- RD
17 -> * * * * * * * * * * * * * * * * | - - * * | <-- WR
LC40 -> * - - - - - - - - - - - - - - * | - - - * | <-- D0
LC38 -> - * - - - - - - - - - - - - * - | - - - * | <-- D1
LC36 -> - - * - - - - - - - - - - * - - | - - - * | <-- D2
LC33 -> - - - * - - - - - - - - * - - - | - - - * | <-- D3
LC45 -> - - - - * - - - - - - * - - - - | - - - * | <-- D4
LC41 -> - - - - - * - - - - * - - - - - | - - - * | <-- D5
LC35 -> - - - - - - * - - * - - - - - - | - - - * | <-- D6
LC37 -> - - - - - - - * * - - - - - - - | - - - * | <-- D7
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\zong\selection.rpt
selection
** EQUATIONS **
A0 : INPUT;
CS : INPUT;
RD : INPUT;
Rx_buf0 : INPUT;
Rx_buf1 : INPUT;
Rx_buf2 : INPUT;
Rx_buf3 : INPUT;
Rx_buf4 : INPUT;
Rx_buf5 : INPUT;
Rx_buf6 : INPUT;
Rx_buf7 : INPUT;
status0 : INPUT;
status1 : INPUT;
status2 : INPUT;
status3 : INPUT;
status4 : INPUT;
status5 : INPUT;
status6 : INPUT;
status7 : INPUT;
WR : INPUT;
~PIN001 : INPUT;
-- Node name is 'D0'
-- Equation name is 'D0', location is LC040, type is bidir.
D0 = TRI(_LC040, GLOBAL(!~PIN001));
_LC040 = LCELL( _EQ001 $ GND);
_EQ001 = A0 & !CS & !RD & status0 & WR
# !A0 & !CS & !RD & Rx_buf0 & WR;
-- Node name is 'D1'
-- Equation name is 'D1', location is LC038, type is bidir.
D1 = TRI(_LC038, GLOBAL(!~PIN001));
_LC038 = LCELL( _EQ002 $ GND);
_EQ002 = A0 & !CS & !RD & status1 & WR
# !A0 & !CS & !RD & Rx_buf1 & WR;
-- Node name is 'D2'
-- Equation name is 'D2', location is LC036, type is bidir.
D2 = TRI(_LC036, GLOBAL(!~PIN001));
_LC036 = LCELL( _EQ003 $ GND);
_EQ003 = A0 & !CS & !RD & status2 & WR
# !A0 & !CS & !RD & Rx_buf2 & WR;
-- Node name is 'D3'
-- Equation name is 'D3', location is LC033, type is bidir.
D3 = TRI(_LC033, GLOBAL(!~PIN001));
_LC033 = LCELL( _EQ004 $ GND);
_EQ004 = A0 & !CS & !RD & status3 & WR
# !A0 & !CS & !RD & Rx_buf3 & WR;
-- Node name is 'D4'
-- Equation name is 'D4', location is LC045, type is bidir.
D4 = TRI(_LC045, GLOBAL(!~PIN001));
_LC045 = LCELL( _EQ005 $ GND);
_EQ005 = A0 & !CS & !RD & status4 & WR
# !A0 & !CS & !RD & Rx_buf4 & WR;
-- Node name is 'D5'
-- Equation name is 'D5', location is LC041, type is bidir.
D5 = TRI(_LC041, GLOBAL(!~PIN001));
_LC041 = LCELL( _EQ006 $ GND);
_EQ006 = A0 & !CS & !RD & status5 & WR
# !A0 & !CS & !RD & Rx_buf5 & WR;
-- Node name is 'D6'
-- Equation name is 'D6', location is LC035, type is bidir.
D6 = TRI(_LC035, GLOBAL(!~PIN001));
_LC035 = LCELL( _EQ007 $ GND);
_EQ007 = A0 & !CS & !RD & status6 & WR
# !A0 & !CS & !RD & Rx_buf6 & WR;
-- Node name is 'D7'
-- Equation name is 'D7', location is LC037, type is bidir.
D7 = TRI(_LC037, GLOBAL(!~PIN001));
_LC037 = LCELL( _EQ008 $ GND);
_EQ008 = A0 & !CS & !RD & status7 & WR
# !A0 & !CS & !RD & Rx_buf7 & WR;
-- Node name is 'Tx_buf0' = '~371~1'
-- Equation name is 'Tx_buf0', location is LC064, type is output.
Tx_buf0 = LCELL( _EQ009 $ GND);
_EQ009 = !CS & D0 & RD & !WR
# Tx_buf0 & WR
# CS & Tx_buf0
# !RD & Tx_buf0
# _LC058;
-- Node name is 'Tx_buf1' = '~362~1'
-- Equation name is 'Tx_buf1', location is LC060, type is output.
Tx_buf1 = LCELL( _EQ010 $ GND);
_EQ010 = !CS & D1 & RD & !WR
# Tx_buf1 & WR
# CS & Tx_buf1
# !RD & Tx_buf1
# _LC063;
-- Node name is 'Tx_buf2' = '~353~1'
-- Equation name is 'Tx_buf2', location is LC051, type is output.
Tx_buf2 = LCELL( _EQ011 $ GND);
_EQ011 = !CS & D2 & RD & !WR
# Tx_buf2 & WR
# CS & Tx_buf2
# !RD & Tx_buf2
# _LC059;
-- Node name is 'Tx_buf3' = '~344~1'
-- Equation name is 'Tx_buf3', location is LC062, type is output.
Tx_buf3 = LCELL( _EQ012 $ GND);
_EQ012 = !CS & D3 & RD & !WR
# Tx_buf3 & WR
# CS & Tx_buf3
# !RD & Tx_buf3
# _LC055;
-- Node name is 'Tx_buf4' = '~335~1'
-- Equation name is 'Tx_buf4', location is LC049, type is output.
Tx_buf4 = LCELL( _EQ013 $ GND);
_EQ013 = !CS & D4 & RD & !WR
# Tx_buf4 & WR
# CS & Tx_buf4
# !RD & Tx_buf4
# _LC050;
-- Node name is 'Tx_buf5' = '~326~1'
-- Equation name is 'Tx_buf5', location is LC061, type is output.
Tx_buf5 = LCELL( _EQ014 $ GND);
_EQ014 = !CS & D5 & RD & !WR
# Tx_buf5 & WR
# CS & Tx_buf5
# !RD & Tx_buf5
# _LC052;
-- Node name is 'Tx_buf6' = '~317~1'
-- Equation name is 'Tx_buf6', location is LC057, type is output.
Tx_buf6 = LCELL( _EQ015 $ GND);
_EQ015 = !CS & D6 & RD & !WR
# Tx_buf6 & WR
# CS & Tx_buf6
# !RD & Tx_buf6
# _LC053;
-- Node name is 'Tx_buf7' = '~308~1'
-- Equation name is 'Tx_buf7', location is LC056, type is output.
Tx_buf7 = LCELL( _EQ016 $ GND);
_EQ016 = !CS & D7 & RD & !WR
# Tx_buf7 & WR
# CS & Tx_buf7
# !RD & Tx_buf7
# _LC054;
-- Node name is '~380~1'
-- Equation name is '~380~1', location is LC043, type is output.
~PIN002 = LCELL( _EQ017 $ VCC);
_EQ017 = !CS & !RD & WR;
-- Node name is '~308~1~2'
-- Equation name is '~308~1~2', location is LC054, type is buried.
-- synthesized logic cell
_LC054 = LCELL( _EQ018 $ GND);
_EQ018 = !CS & D7 & RD & Tx_buf7
# D7 & RD & Tx_buf7 & !WR
# !CS & D7 & Tx_buf7 & !WR;
-- Node name is '~317~1~2'
-- Equation name is '~317~1~2', location is LC053, type is buried.
-- synthesized logic cell
_LC053 = LCELL( _EQ019 $ GND);
_EQ019 = !CS & D6 & RD & Tx_buf6
# D6 & RD & Tx_buf6 & !WR
# !CS & D6 & Tx_buf6 & !WR;
-- Node name is '~326~1~2'
-- Equation name is '~326~1~2', location is LC052, type is buried.
-- synthesized logic cell
_LC052 = LCELL( _EQ020 $ GND);
_EQ020 = !CS & D5 & RD & Tx_buf5
# D5 & RD & Tx_buf5 & !WR
# !CS & D5 & Tx_buf5 & !WR;
-- Node name is '~335~1~2'
-- Equation name is '~335~1~2', location is LC050, type is buried.
-- synthesized logic cell
_LC050 = LCELL( _EQ021 $ GND);
_EQ021 = !CS & D4 & RD & Tx_buf4
# D4 & RD & Tx_buf4 & !WR
# !CS & D4 & Tx_buf4 & !WR;
-- Node name is '~344~1~2'
-- Equation name is '~344~1~2', location is LC055, type is buried.
-- synthesized logic cell
_LC055 = LCELL( _EQ022 $ GND);
_EQ022 = !CS & D3 & RD & Tx_buf3
# D3 & RD & Tx_buf3 & !WR
# !CS & D3 & Tx_buf3 & !WR;
-- Node name is '~353~1~2'
-- Equation name is '~353~1~2', location is LC059, type is buried.
-- synthesized logic cell
_LC059 = LCELL( _EQ023 $ GND);
_EQ023 = !CS & D2 & RD & Tx_buf2
# D2 & RD & Tx_buf2 & !WR
# !CS & D2 & Tx_buf2 & !WR;
-- Node name is '~362~1~2'
-- Equation name is '~362~1~2', location is LC063, type is buried.
-- synthesized logic cell
_LC063 = LCELL( _EQ024 $ GND);
_EQ024 = !CS & D1 & RD & Tx_buf1
# D1 & RD & Tx_buf1 & !WR
# !CS & D1 & Tx_buf1 & !WR;
-- Node name is '~371~1~2'
-- Equation name is '~371~1~2', location is LC058, type is buried.
-- synthesized logic cell
_LC058 = LCELL( _EQ025 $ GND);
_EQ025 = !CS & D0 & RD & Tx_buf0
# D0 & RD & Tx_buf0 & !WR
# !CS & D0 & Tx_buf0 & !WR;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\zong\selection.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:00
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,711K
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