📄 selection.rpt
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Project Information d:\zong\selection.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 09/07/2005 10:32:11
Copyright (C) 1988-2000 Altera Corporation
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***** Project compilation was successful
SELECTION
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
selection
EPM7064LC68-7 21 9 8 25 0 39 %
User Pins: 20 8 8
Project Information d:\zong\selection.rpt
** MULTIPLE PIN CONNECTIONS **
For node name '~380~2' (Same as node '~PIN001')
For node name '~380~1' (Same as node '~PIN002')
Connect: {selection@68, selection@45}
Device-Specific Information: d:\zong\selection.rpt
selection
***** Logic for device 'selection' compiled without errors.
Device: EPM7064LC68-7
Device Options:
Turbo Bit = ON
Security Bit = OFF
MultiVolt I/O = OFF
R s s R ~ T T T T
x t t x V P x x x x
_ a a _ C I _ _ V _ _
b t t b C N b b C b b
u u G u u I G G 0 G G u u C u u
C f s N s f N N N 0 N N f f I f f
S 1 2 D 3 2 T D D 1 D D 0 3 O 5 1
-----------------------------------------------------_
/ 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 |
RESERVED | 10 60 | RESERVED
VCCIO | 11 59 | Tx_buf6
RD | 12 58 | GND
status1 | 13 57 | Tx_buf7
status0 | 14 56 | RESERVED
Rx_buf7 | 15 55 | RESERVED
GND | 16 54 | RESERVED
WR | 17 53 | VCCIO
RESERVED | 18 EPM7064LC68-7 52 | Tx_buf2
Rx_buf6 | 19 51 | Tx_buf4
status7 | 20 50 | RESERVED
VCCIO | 21 49 | RESERVED
status6 | 22 48 | GND
status5 | 23 47 | D4
RESERVED | 24 46 | RESERVED
Rx_buf5 | 25 45 | ~PIN002
GND | 26 44 | D5
|_ 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 _|
------------------------------------------------------
s R R A V R R G V D D G D D D D V
t x x 0 C x E N C 3 6 N 2 7 1 0 C
a _ _ C _ S D C D C
t b b I b E I I
u u u O u R N O
s f f f V T
4 4 3 0 E
D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: d:\zong\selection.rpt
selection
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 10/12( 83%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 0/16( 0%) 10/12( 83%) 0/16( 0%) 0/36( 0%)
C: LC33 - LC48 9/16( 56%) 9/12( 75%) 0/16( 0%) 20/36( 55%)
D: LC49 - LC64 16/16(100%) 8/12( 66%) 8/16( 50%) 27/36( 75%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 37/48 ( 77%)
Total logic cells used: 25/64 ( 39%)
Total shareable expanders used: 0/64 ( 0%)
Total Turbo logic cells used: 25/64 ( 39%)
Total shareable expanders not available (n/a): 8/64 ( 12%)
Average fan-in: 5.88
Total fan-in: 147
Total input pins required: 21
Total output pins required: 9
Total bidirectional pins required: 8
Total logic cells required: 25
Total flipflops required: 0
Total product terms required: 81
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 0
Synthesized logic cells: 16/ 64 ( 25%)
Device-Specific Information: d:\zong\selection.rpt
selection
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
30 (20) (B) INPUT 0 0 0 0 0 8 0 A0
9 (11) (A) INPUT 0 0 0 0 0 17 8 CS
42 40 C BIDIR 0 0 0 6 0 1 1 D0
41 38 C BIDIR 0 0 0 6 0 1 1 D1
39 36 C BIDIR 0 0 0 6 0 1 1 D2
36 33 C BIDIR 0 0 0 6 0 1 1 D3
47 45 C BIDIR 0 0 0 6 0 1 1 D4
44 41 C BIDIR 0 0 0 6 0 1 1 D5
37 35 C BIDIR 0 0 0 6 0 1 1 D6
40 37 C BIDIR 0 0 0 6 0 1 1 D7
68 - - INPUT G s 0 0 0 0 0 0 0 ~PIN001
12 (8) (A) INPUT 0 0 0 0 0 17 8 RD
32 (19) (B) INPUT 0 0 0 0 0 1 0 Rx_buf0
8 (12) (A) INPUT 0 0 0 0 0 1 0 Rx_buf1
4 (16) (A) INPUT 0 0 0 0 0 1 0 Rx_buf2
29 (21) (B) INPUT 0 0 0 0 0 1 0 Rx_buf3
28 (22) (B) INPUT 0 0 0 0 0 1 0 Rx_buf4
25 (25) (B) INPUT 0 0 0 0 0 1 0 Rx_buf5
19 (32) (B) INPUT 0 0 0 0 0 1 0 Rx_buf6
15 (4) (A) INPUT 0 0 0 0 0 1 0 Rx_buf7
14 (5) (A) INPUT 0 0 0 0 0 1 0 status0
13 (6) (A) INPUT 0 0 0 0 0 1 0 status1
7 (13) (A) INPUT 0 0 0 0 0 1 0 status2
5 (14) (A) INPUT 0 0 0 0 0 1 0 status3
27 (24) (B) INPUT 0 0 0 0 0 1 0 status4
23 (28) (B) INPUT 0 0 0 0 0 1 0 status5
22 (29) (B) INPUT 0 0 0 0 0 1 0 status6
20 (30) (B) INPUT 0 0 0 0 0 1 0 status7
17 (3) (A) INPUT 0 0 0 0 0 17 8 WR
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\zong\selection.rpt
selection
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
42 40 C TRI t 0 0 0 6 0 1 1 D0
41 38 C TRI t 0 0 0 6 0 1 1 D1
39 36 C TRI t 0 0 0 6 0 1 1 D2
36 33 C TRI t 0 0 0 6 0 1 1 D3
47 45 C TRI t 0 0 0 6 0 1 1 D4
44 41 C TRI t 0 0 0 6 0 1 1 D5
37 35 C TRI t 0 0 0 6 0 1 1 D6
40 37 C TRI t 0 0 0 6 0 1 1 D7
45 43 C OUTPUT t 0 0 0 3 0 0 0 ~PIN002
65 64 D OUTPUT s t 1 0 1 3 3 1 1 Tx_buf0
61 60 D OUTPUT s t 1 0 1 3 3 1 1 Tx_buf1
52 51 D OUTPUT s t 1 0 1 3 3 1 1 Tx_buf2
64 62 D OUTPUT s t 1 0 1 3 3 1 1 Tx_buf3
51 49 D OUTPUT s t 1 0 1 3 3 1 1 Tx_buf4
62 61 D OUTPUT s t 1 0 1 3 3 1 1 Tx_buf5
59 57 D OUTPUT s t 1 0 1 3 3 1 1 Tx_buf6
57 56 D OUTPUT s t 1 0 1 3 3 1 1 Tx_buf7
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\zong\selection.rpt
selection
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(56) 54 D LCELL s t 0 0 0 3 2 1 0 ~308~1~2
(55) 53 D LCELL s t 0 0 0 3 2 1 0 ~317~1~2
(54) 52 D LCELL s t 0 0 0 3 2 1 0 ~326~1~2
- 50 D LCELL s t 0 0 0 3 2 1 0 ~335~1~2
- 55 D LCELL s t 0 0 0 3 2 1 0 ~344~1~2
(60) 59 D LCELL s t 0 0 0 3 2 1 0 ~353~1~2
- 63 D LCELL s t 0 0 0 3 2 1 0 ~362~1~2
- 58 D LCELL s t 0 0 0 3 2 1 0 ~371~1~2
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\zong\selection.rpt
selection
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+----------------- LC40 D0
| +--------------- LC38 D1
| | +------------- LC36 D2
| | | +----------- LC33 D3
| | | | +--------- LC45 D4
| | | | | +------- LC41 D5
| | | | | | +----- LC35 D6
| | | | | | | +--- LC37 D7
| | | | | | | | +- LC43 ~PIN002
| | | | | | | | |
| | | | | | | | | Other LABs fed by signals
| | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | A B C D | Logic cells that feed LAB 'C':
Pin
30 -> * * * * * * * * - | - - * - | <-- A0
9 -> * * * * * * * * * | - - * * | <-- CS
68 -> - - - - - - - - - | - - - - | <-- ~PIN001
12 -> * * * * * * * * * | - - * * | <-- RD
32 -> * - - - - - - - - | - - * - | <-- Rx_buf0
8 -> - * - - - - - - - | - - * - | <-- Rx_buf1
4 -> - - * - - - - - - | - - * - | <-- Rx_buf2
29 -> - - - * - - - - - | - - * - | <-- Rx_buf3
28 -> - - - - * - - - - | - - * - | <-- Rx_buf4
25 -> - - - - - * - - - | - - * - | <-- Rx_buf5
19 -> - - - - - - * - - | - - * - | <-- Rx_buf6
15 -> - - - - - - - * - | - - * - | <-- Rx_buf7
14 -> * - - - - - - - - | - - * - | <-- status0
13 -> - * - - - - - - - | - - * - | <-- status1
7 -> - - * - - - - - - | - - * - | <-- status2
5 -> - - - * - - - - - | - - * - | <-- status3
27 -> - - - - * - - - - | - - * - | <-- status4
23 -> - - - - - * - - - | - - * - | <-- status5
22 -> - - - - - - * - - | - - * - | <-- status6
20 -> - - - - - - - * - | - - * - | <-- status7
17 -> * * * * * * * * * | - - * * | <-- WR
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\zong\selection.rpt
selection
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+------------------------------- LC64 Tx_buf0
| +----------------------------- LC60 Tx_buf1
| | +--------------------------- LC51 Tx_buf2
| | | +------------------------- LC62 Tx_buf3
| | | | +----------------------- LC49 Tx_buf4
| | | | | +--------------------- LC61 Tx_buf5
| | | | | | +------------------- LC57 Tx_buf6
| | | | | | | +----------------- LC56 Tx_buf7
| | | | | | | | +--------------- LC54 ~308~1~2
| | | | | | | | | +------------- LC53 ~317~1~2
| | | | | | | | | | +----------- LC52 ~326~1~2
| | | | | | | | | | | +--------- LC50 ~335~1~2
| | | | | | | | | | | | +------- LC55 ~344~1~2
| | | | | | | | | | | | | +----- LC59 ~353~1~2
| | | | | | | | | | | | | | +--- LC63 ~362~1~2
| | | | | | | | | | | | | | | +- LC58 ~371~1~2
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'D':
LC64 -> * - - - - - - - - - - - - - - * | - - - * | <-- Tx_buf0
LC60 -> - * - - - - - - - - - - - - * - | - - - * | <-- Tx_buf1
LC51 -> - - * - - - - - - - - - - * - - | - - - * | <-- Tx_buf2
LC62 -> - - - * - - - - - - - - * - - - | - - - * | <-- Tx_buf3
LC49 -> - - - - * - - - - - - * - - - - | - - - * | <-- Tx_buf4
LC61 -> - - - - - * - - - - * - - - - - | - - - * | <-- Tx_buf5
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