hao1.vhd

本程序是用VHDL语言实现异步通信控制器

LIBRARY ieee; 
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity hao1 is
	port(reset,TXC,RXC,RXD:IN STD_LOGIC;
			   CS,A0,RD,WR:IN STD_LOGIC;
			       IRQ,TXD:OUT STD_LOGIC;
					 --TB,RB:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
						 D:INOUT STD_LOGIC_VECTOR(7 DOWNTO 0));
end;
architecture behave of hao1 is
signal FE,PE,OVERFLOW,RBF,TBE:STD_LOGIC;
signal	ERXE,ETBE,ERBF:STD_LOGIC;
signal LDRB,RXEN,W_r,LDSR,SCLK,Td,D_OUT:STD_LOGIC;
signal TX_BUF,RX_BUF,STATUS:STD_LOGIC_VECTOR(7 DOWNTO 0);

COMPONENT send
	port(CS,A0,RD,WR:in std_logic;
		 TXC,reset:in std_logic;
		 d_in:in std_logic_vector(7 downto 0);
		 D_OUT,TBE_out:out std_logic);
END COMPONENT;
COMPONENT receiver
	port(CS,A0,RD,WR:in std_logic;
		 RXC,RXD,RESET,TBE:in std_logic;
		 SCLK,FE,PE,RBF,OVERFLOW:out std_logic;
		 RX_buf:out std_logic_vector(7 downto 0));
end COMPONENT;
component selection
	port(CS,A0,RD,WR:IN STD_LOGIC;
		 Rx_buf:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
		 status:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
		 Tx_buf:OUT STD_LOGIC_vector(7 DOWNTO 0);
		 D:INOUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END component;
COMPONENT reg
	port(reset,CS,A0,RD,WR:IN STD_LOGIC;
		 FE,PE,OVERFLOW,RBF,TBE:in STD_LOGIC;
			IRQ:OUT STD_LOGIC;
		 din:in std_logic_vector(7 downto 0);
		 status:out std_logic_vector(7 downto 0));
end COMPONENT;
begin
	u1:selection port map(CS,A0,RD,WR,Rx_buf,status,Tx_buf,D);
	u2:send port map(CS,A0,RD,WR,TXC,reset,Tx_buf,TXD,TBE);
	u3:reg port map(reset,CS,A0,RD,WR,FE,PE,OVERFLOW,RBF,TBE,IRQ,TX_buf,status);
	u4:receiver port map(CS,A0,RD,WR,RXC,RXD,RESET,TBE,SCLK,FE,PE,RBF,OVERFLOW,RX_buf);
	--TB<=tX_BUF;RB<=RX_BUF;
END;