shifter.rpt

本程序是用VHDL语言实现异步通信控制器

* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                               d:\zong\shifter.rpt
shifter

** EQUATIONS **

A0       : INPUT;
LDRB     : INPUT;
LDSR     : INPUT;
RXD      : INPUT;
RXEN     : INPUT;
TBE      : INPUT;

-- Node name is 'OVERFLOW' = ':17' 
-- Equation name is 'OVERFLOW', type is output 
 OVERFLOW = DFFE( _EQ001 $  GND,  LDRB,  VCC,  VCC,  VCC);
  _EQ001 =  A0 &  LDRB;

-- Node name is 'PE' 
-- Equation name is 'PE', location is LC010, type is output.
 PE      = LCELL( _EQ002 $  _EQ003);
  _EQ002 = !A0 & !_LC023 &  LDRB &  TBE &  temp7 &  _X001 &  _X002 &  _X003 & 
              _X004 &  _X005 &  _X006
         # !A0 &  _LC023 &  LDRB &  TBE & !temp7 &  _X001 &  _X002 &  _X003 & 
              _X004 &  _X005 &  _X006;
  _X001  = EXP(!_LC022 & !_LC023);
  _X002  = EXP(!A0 &  TBE &  temp8);
  _X003  = EXP(!A0 &  _LC023 &  TBE &  temp7 &  temp8);
  _X004  = EXP(!A0 &  _LC023 &  TBE &  temp7 &  _X007);
  _X005  = EXP(!A0 & !_LC023 &  TBE & !temp7 &  temp8);
  _X006  = EXP(!A0 & !_LC023 &  TBE & !temp7 &  _X007);
  _X007  = EXP(!A0 &  TBE);
  _EQ003 = !A0 &  LDRB &  _X001 &  _X003 &  _X004 &  _X005 &  _X006;
  _X001  = EXP(!_LC022 & !_LC023);
  _X003  = EXP(!A0 &  _LC023 &  TBE &  temp7 &  temp8);
  _X004  = EXP(!A0 &  _LC023 &  TBE &  temp7 &  _X007);
  _X005  = EXP(!A0 & !_LC023 &  TBE & !temp7 &  temp8);
  _X006  = EXP(!A0 & !_LC023 &  TBE & !temp7 &  _X007);
  _X007  = EXP(!A0 &  TBE);

-- Node name is 'RBF' 
-- Equation name is 'RBF', location is LC009, type is output.
 RBF     = LCELL( LDRB $  GND);

-- Node name is 'RX_buf0' 
-- Equation name is 'RX_buf0', location is LC030, type is output.
 RX_buf0 = LCELL( _EQ004 $  GND);
  _EQ004 =  LDRB &  temp1;

-- Node name is 'RX_buf1' 
-- Equation name is 'RX_buf1', location is LC026, type is output.
 RX_buf1 = LCELL( _EQ005 $  GND);
  _EQ005 =  LDRB &  temp2;

-- Node name is 'RX_buf2' 
-- Equation name is 'RX_buf2', location is LC027, type is output.
 RX_buf2 = LCELL( _EQ006 $  GND);
  _EQ006 =  LDRB &  temp3;

-- Node name is 'RX_buf3' 
-- Equation name is 'RX_buf3', location is LC028, type is output.
 RX_buf3 = LCELL( _EQ007 $  GND);
  _EQ007 =  LDRB &  temp4;

-- Node name is 'RX_buf4' 
-- Equation name is 'RX_buf4', location is LC031, type is output.
 RX_buf4 = LCELL( _EQ008 $  GND);
  _EQ008 =  LDRB &  temp5;

-- Node name is 'RX_buf5' 
-- Equation name is 'RX_buf5', location is LC024, type is output.
 RX_buf5 = LCELL( _EQ009 $  GND);
  _EQ009 =  LDRB &  temp6;

-- Node name is 'RX_buf6' 
-- Equation name is 'RX_buf6', location is LC008, type is output.
 RX_buf6 = LCELL( _EQ010 $  GND);
  _EQ010 =  LDRB &  temp7;

-- Node name is 'RX_buf7' 
-- Equation name is 'RX_buf7', location is LC007, type is output.
 RX_buf7 = LCELL( _EQ011 $  GND);
  _EQ011 =  LDRB &  temp8;

-- Node name is ':26' = 'temp1' 
-- Equation name is 'temp1', location is LC021, type is buried.
temp1    = DFFE( _EQ012 $ !LDRB, GLOBAL( RXEN),  VCC,  VCC,  VCC);
  _EQ012 = !LDRB & !LDSR & !temp2
         #  LDRB &  temp1;

-- Node name is ':25' = 'temp2' 
-- Equation name is 'temp2', location is LC020, type is buried.
temp2    = DFFE( _EQ013 $ !LDRB, GLOBAL( RXEN),  VCC,  VCC,  VCC);
  _EQ013 = !LDRB & !LDSR & !temp3
         #  LDRB &  temp2;

-- Node name is ':24' = 'temp3' 
-- Equation name is 'temp3', location is LC019, type is buried.
temp3    = DFFE( _EQ014 $ !LDRB, GLOBAL( RXEN),  VCC,  VCC,  VCC);
  _EQ014 = !LDRB & !LDSR & !temp4
         #  LDRB &  temp3;

-- Node name is ':23' = 'temp4' 
-- Equation name is 'temp4', location is LC018, type is buried.
temp4    = DFFE( _EQ015 $ !LDRB, GLOBAL( RXEN),  VCC,  VCC,  VCC);
  _EQ015 = !LDRB & !LDSR & !temp5
         #  LDRB &  temp4;

-- Node name is ':22' = 'temp5' 
-- Equation name is 'temp5', location is LC017, type is buried.
temp5    = DFFE( _EQ016 $ !LDRB, GLOBAL( RXEN),  VCC,  VCC,  VCC);
  _EQ016 = !LDRB & !LDSR & !temp6
         #  LDRB &  temp5;

-- Node name is ':21' = 'temp6' 
-- Equation name is 'temp6', location is LC001, type is buried.
temp6    = DFFE( _EQ017 $ !LDRB, GLOBAL( RXEN),  VCC,  VCC,  VCC);
  _EQ017 = !LDRB & !LDSR & !temp7
         #  LDRB &  temp6;

-- Node name is ':20' = 'temp7' 
-- Equation name is 'temp7', location is LC004, type is buried.
temp7    = DFFE( _EQ018 $ !LDRB, GLOBAL( RXEN),  VCC,  VCC,  VCC);
  _EQ018 = !LDRB & !LDSR & !temp8
         #  LDRB &  temp7;

-- Node name is ':19' = 'temp8' 
-- Equation name is 'temp8', location is LC005, type is buried.
temp8    = DFFE( _EQ019 $ !LDRB, GLOBAL( RXEN),  VCC,  VCC,  VCC);
  _EQ019 = !LDRB & !LDSR & !RXD
         #  LDRB &  temp8;

-- Node name is '~659~1' 
-- Equation name is '~659~1', location is LC022, type is buried.
-- synthesized logic cell 
_LC022   = LCELL( _EQ020 $  GND);
  _EQ020 = !A0 &  TBE;

-- Node name is '~735~1' 
-- Equation name is '~735~1', location is LC023, type is buried.
-- synthesized logic cell 
_LC023   = LCELL( _EQ021 $  _EQ022);
  _EQ021 = !A0 & !_LC006 & !_LC025 & !_LC029 &  TBE &  temp1 &  temp2 & 
              temp3 &  temp4 &  temp5 &  temp6 &  _X008 &  _X009 &  _X010 & 
              _X011 &  _X012 &  _X013 &  _X014 &  _X015 &  _X016 &  _X017 & 
              _X018 &  _X019 &  _X020
         # !A0 & !_LC006 & !_LC025 & !_LC029 &  TBE &  temp1 &  temp2 & 
              temp3 &  temp4 & !temp5 & !temp6 &  _X008 &  _X009 &  _X010 & 
              _X011 &  _X012 &  _X013 &  _X014 &  _X015 &  _X016 &  _X017 & 
              _X018 &  _X019 &  _X020
         # !A0 & !_LC006 & !_LC025 & !_LC029 &  TBE &  temp1 &  temp2 & 
              temp3 & !temp4 &  temp5 & !temp6 &  _X008 &  _X009 &  _X010 & 
              _X011 &  _X012 &  _X013 &  _X014 &  _X015 &  _X016 &  _X017 & 
              _X018 &  _X019 &  _X020
         # !A0 & !_LC006 & !_LC025 & !_LC029 &  TBE &  temp1 &  temp2 & 
             !temp3 &  temp4 &  temp5 & !temp6 &  _X008 &  _X009 &  _X010 & 
              _X011 &  _X012 &  _X013 &  _X014 &  _X015 &  _X016 &  _X017 & 
              _X018 &  _X019 &  _X020;
  _X008  = EXP(!temp1 &  temp2 & !temp3 & !temp4 & !temp5 &  temp6);
  _X009  = EXP( temp1 & !temp2 & !temp3 & !temp4 &  temp5 & !temp6);
  _X010  = EXP(!temp1 &  temp2 &  temp3 & !temp4 & !temp5 & !temp6);
  _X011  = EXP(!temp1 & !temp2 & !temp3 & !temp4 & !temp5 & !temp6);
  _X012  = EXP(!temp1 & !temp2 & !temp3 & !temp4 &  temp5 &  temp6);
  _X013  = EXP(!temp1 & !temp2 & !temp3 &  temp4 & !temp5 &  temp6);
  _X014  = EXP(!temp1 & !temp2 &  temp3 & !temp4 & !temp5 &  temp6);
  _X015  = EXP(!temp1 &  temp2 & !temp3 &  temp4 & !temp5 & !temp6);
  _X016  = EXP( temp1 & !temp2 & !temp3 & !temp4 & !temp5 &  temp6);
  _X017  = EXP(!temp1 & !temp2 & !temp3 &  temp4 &  temp5 & !temp6);
  _X018  = EXP(!temp1 & !temp2 &  temp3 & !temp4 &  temp5 & !temp6);
  _X019  = EXP(!temp1 & !temp2 &  temp3 &  temp4 & !temp5 & !temp6);
  _X020  = EXP(!temp1 &  temp2 & !temp3 & !temp4 &  temp5 & !temp6);
  _EQ022 = !A0 & !_LC006 & !_LC025 & !_LC029 &  TBE &  _X008 &  _X009 & 
              _X010 &  _X011 &  _X012 &  _X013 &  _X014 &  _X015 &  _X016 & 
              _X017 &  _X018 &  _X019 &  _X020;
  _X008  = EXP(!temp1 &  temp2 & !temp3 & !temp4 & !temp5 &  temp6);
  _X009  = EXP( temp1 & !temp2 & !temp3 & !temp4 &  temp5 & !temp6);
  _X010  = EXP(!temp1 &  temp2 &  temp3 & !temp4 & !temp5 & !temp6);
  _X011  = EXP(!temp1 & !temp2 & !temp3 & !temp4 & !temp5 & !temp6);
  _X012  = EXP(!temp1 & !temp2 & !temp3 & !temp4 &  temp5 &  temp6);
  _X013  = EXP(!temp1 & !temp2 & !temp3 &  temp4 & !temp5 &  temp6);
  _X014  = EXP(!temp1 & !temp2 &  temp3 & !temp4 & !temp5 &  temp6);
  _X015  = EXP(!temp1 &  temp2 & !temp3 &  temp4 & !temp5 & !temp6);
  _X016  = EXP( temp1 & !temp2 & !temp3 & !temp4 & !temp5 &  temp6);
  _X017  = EXP(!temp1 & !temp2 & !temp3 &  temp4 &  temp5 & !temp6);
  _X018  = EXP(!temp1 & !temp2 &  temp3 & !temp4 &  temp5 & !temp6);
  _X019  = EXP(!temp1 & !temp2 &  temp3 &  temp4 & !temp5 & !temp6);
  _X020  = EXP(!temp1 &  temp2 & !temp3 & !temp4 &  temp5 & !temp6);

-- Node name is '~735~2' 
-- Equation name is '~735~2', location is LC006, type is buried.
-- synthesized logic cell 
_LC006   = LCELL( _EQ023 $  GND);
  _EQ023 =  temp1 &  temp2 &  temp3 & !temp4 & !temp5 &  temp6
         #  temp1 &  temp2 & !temp3 &  temp4 & !temp5 &  temp6
         #  temp1 &  temp2 & !temp3 & !temp4 &  temp5 &  temp6
         #  temp1 & !temp2 &  temp3 &  temp4 &  temp5 & !temp6
         #  temp1 & !temp2 &  temp3 &  temp4 & !temp5 &  temp6;

-- Node name is '~735~3' 
-- Equation name is '~735~3', location is LC025, type is buried.
-- synthesized logic cell 
_LC025   = LCELL( _EQ024 $  GND);
  _EQ024 =  temp1 & !temp2 &  temp3 & !temp4 &  temp5 &  temp6
         #  temp1 & !temp2 & !temp3 &  temp4 &  temp5 &  temp6
         # !temp1 &  temp2 &  temp3 &  temp4 &  temp5 & !temp6
         # !temp1 &  temp2 &  temp3 &  temp4 & !temp5 &  temp6
         # !temp1 &  temp2 &  temp3 & !temp4 &  temp5 &  temp6;

-- Node name is '~735~4' 
-- Equation name is '~735~4', location is LC029, type is buried.
-- synthesized logic cell 
_LC029   = LCELL( _EQ025 $  GND);
  _EQ025 = !temp1 &  temp2 & !temp3 &  temp4 &  temp5 &  temp6
         # !temp1 & !temp2 &  temp3 &  temp4 &  temp5 &  temp6
         #  temp1 &  temp2 & !temp3 & !temp4 & !temp5 & !temp6
         #  temp1 & !temp2 &  temp3 & !temp4 & !temp5 & !temp6
         #  temp1 & !temp2 & !temp3 &  temp4 & !temp5 & !temp6;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                        d:\zong\shifter.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:01
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 6,133K