📄 shifter.rpt
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Project Information d:\zong\shifter.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 09/07/2005 11:48:21
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
SHIFTER
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
shifter EPM7032LC44-6 6 11 0 24 20 75 %
User Pins: 6 11 0
Project Information d:\zong\shifter.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'RXEN' chosen for auto global Clock
Device-Specific Information: d:\zong\shifter.rpt
shifter
***** Logic for device 'shifter' compiled without errors.
Device: EPM7032LC44-6
Device Options:
Turbo Bit = ON
Security Bit = OFF
R R
E E
S S
E E
L L R R R
D D V G G G X G V V
S R A C N N N E N E E
R B 0 C D D D N D D D
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
TBE | 7 39 | RESERVED
RXD | 8 38 | RESERVED
RESERVED | 9 37 | RESERVED
GND | 10 36 | RESERVED
RX_buf7 | 11 35 | VCC
RX_buf6 | 12 EPM7032LC44-6 34 | RESERVED
RBF | 13 33 | RX_buf5
PE | 14 32 | RESERVED
VCC | 15 31 | RX_buf1
RESERVED | 16 30 | GND
RESERVED | 17 29 | RX_buf2
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
R R R R G V O R R R R
E E E E N C V X X E X
S S S S D C E _ _ S _
E E E E R b b E b
R R R R F u u R u
V V V V L f f V f
E E E E O 4 0 E 3
D D D D W D
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: d:\zong\shifter.rpt
shifter
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 8/16( 50%) 9/16( 56%) 8/16( 50%) 15/36( 41%)
B: LC17 - LC32 16/16(100%) 7/16( 43%) 16/16(100%) 13/36( 36%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 16/32 ( 50%)
Total logic cells used: 24/32 ( 75%)
Total shareable expanders used: 20/32 ( 62%)
Total Turbo logic cells used: 24/32 ( 75%)
Total shareable expanders not available (n/a): 4/32 ( 12%)
Average fan-in: 4.04
Total fan-in: 97
Total input pins required: 6
Total output pins required: 11
Total bidirectional pins required: 0
Total logic cells required: 24
Total flipflops required: 9
Total product terms required: 79
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 20
Synthesized logic cells: 5/ 32 ( 15%)
Device-Specific Information: d:\zong\shifter.rpt
shifter
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
4 (1) (A) INPUT 0 0 0 0 0 2 2 A0
5 (2) (A) INPUT 0 0 0 0 0 11 8 LDRB
6 (3) (A) INPUT 0 0 0 0 0 0 8 LDSR
8 (5) (A) INPUT 0 0 0 0 0 0 1 RXD
43 - - INPUT G 0 0 0 0 0 0 0 RXEN
7 (4) (A) INPUT 0 0 0 0 0 1 2 TBE
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\zong\shifter.rpt
shifter
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
24 32 B FF t 0 0 0 2 0 0 0 OVERFLOW
14 10 A OUTPUT t 7 0 0 3 4 0 0 PE
13 9 A OUTPUT t 0 0 0 1 0 0 0 RBF
26 30 B OUTPUT t 0 0 0 1 1 0 0 RX_buf0
31 26 B OUTPUT t 0 0 0 1 1 0 0 RX_buf1
29 27 B OUTPUT t 0 0 0 1 1 0 0 RX_buf2
28 28 B OUTPUT t 0 0 0 1 1 0 0 RX_buf3
25 31 B OUTPUT t 0 0 0 1 1 0 0 RX_buf4
33 24 B OUTPUT t 0 0 0 1 1 0 0 RX_buf5
12 8 A OUTPUT t 0 0 0 1 1 0 0 RX_buf6
11 7 A OUTPUT t 0 0 0 1 1 0 0 RX_buf7
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\zong\shifter.rpt
shifter
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(8) 5 A DFFE + t 0 0 0 3 1 2 2 temp8 (:19)
(7) 4 A DFFE + t 0 0 0 2 2 2 2 temp7 (:20)
(4) 1 A DFFE + t 0 0 0 2 2 1 6 temp6 (:21)
(41) 17 B DFFE + t 0 0 0 2 2 1 6 temp5 (:22)
(40) 18 B DFFE + t 0 0 0 2 2 1 6 temp4 (:23)
(39) 19 B DFFE + t 0 0 0 2 2 1 6 temp3 (:24)
(38) 20 B DFFE + t 0 0 0 2 2 1 6 temp2 (:25)
(37) 21 B DFFE + t 0 0 0 2 2 1 5 temp1 (:26)
(36) 22 B SOFT s t 0 0 0 2 0 1 0 ~659~1
(34) 23 B SOFT s t 14 0 1 2 9 1 0 ~735~1
(9) 6 A SOFT s t 1 0 1 0 6 0 1 ~735~2
(32) 25 B SOFT s t 1 0 1 0 6 0 1 ~735~3
(27) 29 B SOFT s t 1 0 1 0 6 0 1 ~735~4
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\zong\shifter.rpt
shifter
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+--------------- LC10 PE
| +------------- LC9 RBF
| | +----------- LC8 RX_buf6
| | | +--------- LC7 RX_buf7
| | | | +------- LC5 temp8
| | | | | +----- LC4 temp7
| | | | | | +--- LC1 temp6
| | | | | | | +- LC6 ~735~2
| | | | | | | |
| | | | | | | | Other LABs fed by signals
| | | | | | | | that feed LAB 'A'
LC | | | | | | | | | A B | Logic cells that feed LAB 'A':
LC5 -> * - - * * * - - | * - | <-- temp8
LC4 -> * - * - - * * - | * - | <-- temp7
LC1 -> - - - - - - * * | * * | <-- temp6
Pin
4 -> * - - - - - - - | * * | <-- A0
5 -> * * * * * * * - | * * | <-- LDRB
6 -> - - - - * * * - | * * | <-- LDSR
8 -> - - - - * - - - | * - | <-- RXD
43 -> - - - - - - - - | - - | <-- RXEN
7 -> * - - - - - - - | * * | <-- TBE
LC17 -> - - - - - - - * | * * | <-- temp5
LC18 -> - - - - - - - * | * * | <-- temp4
LC19 -> - - - - - - - * | * * | <-- temp3
LC20 -> - - - - - - - * | * * | <-- temp2
LC21 -> - - - - - - - * | * * | <-- temp1
LC22 -> * - - - - - - - | * - | <-- ~659~1
LC23 -> * - - - - - - - | * - | <-- ~735~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\zong\shifter.rpt
shifter
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC32 OVERFLOW
| +----------------------------- LC30 RX_buf0
| | +--------------------------- LC26 RX_buf1
| | | +------------------------- LC27 RX_buf2
| | | | +----------------------- LC28 RX_buf3
| | | | | +--------------------- LC31 RX_buf4
| | | | | | +------------------- LC24 RX_buf5
| | | | | | | +----------------- LC17 temp5
| | | | | | | | +--------------- LC18 temp4
| | | | | | | | | +------------- LC19 temp3
| | | | | | | | | | +----------- LC20 temp2
| | | | | | | | | | | +--------- LC21 temp1
| | | | | | | | | | | | +------- LC22 ~659~1
| | | | | | | | | | | | | +----- LC23 ~735~1
| | | | | | | | | | | | | | +--- LC25 ~735~3
| | | | | | | | | | | | | | | +- LC29 ~735~4
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC17 -> - - - - - * - * * - - - - * * * | * * | <-- temp5
LC18 -> - - - - * - - - * * - - - * * * | * * | <-- temp4
LC19 -> - - - * - - - - - * * - - * * * | * * | <-- temp3
LC20 -> - - * - - - - - - - * * - * * * | * * | <-- temp2
LC21 -> - * - - - - - - - - - * - * * * | * * | <-- temp1
LC25 -> - - - - - - - - - - - - - * - - | - * | <-- ~735~3
LC29 -> - - - - - - - - - - - - - * - - | - * | <-- ~735~4
Pin
4 -> * - - - - - - - - - - - * * - - | * * | <-- A0
5 -> * * * * * * * * * * * * - - - - | * * | <-- LDRB
6 -> - - - - - - - * * * * * - - - - | * * | <-- LDSR
43 -> - - - - - - - - - - - - - - - - | - - | <-- RXEN
7 -> - - - - - - - - - - - - * * - - | * * | <-- TBE
LC1 -> - - - - - - * * - - - - - * * * | * * | <-- temp6
LC6 -> - - - - - - - - - - - - - * - - | - * | <-- ~735~2
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