receiver.vhd

来自「本程序是用VHDL语言实现异步通信控制器」· VHDL 代码 · 共 29 行

LIBRARY ieee; 
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity receiver is
	port(CS,A0,RD,WR:in std_logic;
		 RXC,RXD,RESET,TBE:in std_logic;
		 SCLK,FE,PE,RBF,OVERFLOW:out std_logic;
		 RX_buf:out std_logic_vector(7 downto 0));
end;
architecture behave of receiver is
signal LDSR,LDRB,RXEN:std_logic;
component control
	port(CS,A0,RD,WR:in std_logic;
		 RXC,RXD,RESET:IN STD_LOGIC;
		 LDSR,LDRB,RXEN,SCLK,FE:OUT STD_LOGIC);
end component;
component shifter
	port(A0:in std_logic;
		 RXD,LDRB,LDSR,RXEN,TBE:in std_logic;
		 RX_buf:out std_logic_vector(7 downto 0);
		 PE,RBF,OVERFLOW:out std_logic);
end component;
begin
	u1:control port map(CS,A0,RD,WR,RXC,RXD,RESET,LDSR,LDRB,RXEN,SCLK,FE);
	u2:shifter port map(A0,RXD,LDRB,LDSR,RXEN,TBE,RX_buf,PE,RBF,OVERFLOW);
end;