asynchronous.vhd

来自「本程序是用VHDL语言实现异步通信控制器」· VHDL 代码 · 共 44 行

LIBRARY ieee; 
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity asynchronous is
	port(reset,TXC,RXC,RXD:IN STD_LOGIC;
			CS,A0,RD,WR:IN STD_LOGIC;
			TXD:OUT STD_LOGIC;
			D:INOUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END;
ARCHITECTURE behavior of asynchronous is
signal FE,PE,OVERFLOW,RBF,TBE:STD_LOGIC;
signal	ERXE,ETBE,ERBF:STD_LOGIC;
signal LDRB,RXEN,W_r,LDSR,SCLK:STD_LOGIC;
signal RX_buf:STD_LOGIC_VECTOR(7 DOWNTO 0) :="00000000";
COMPONENT communication
	port(reset:IN STD_LOGIC;
			CS,A0,RD,WR:IN STD_LOGIC;
			W_r:OUT STD_LOGIC;
			D:INOUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT;
COMPONENT send
	port(TXC,reset,W_r:in std_logic;
		 d_in:in std_logic_vector(7 downto 0);
		 D_OUT,TBE_out:out std_logic);
END COMPONENT;
COMPONENT control
	port(RXC,RXD,RESET:IN STD_LOGIC;
		 LDSR,LDRB,RXEN,SCLK,FE:OUT STD_LOGIC);
END COMPONENT;
COMPONENT shifter
	port(RXD,LDRB,LDSR,RXEN,TBE,W_r:in std_logic;
		 data:out std_logic_vector(7 downto 0);
		 PE:out std_logic);
END COMPONENT;
begin
	--TXD<=RXD;
	u1:communication PORT MAP(RXD,CS,A0,RD,WR,W_r,D);
	u2:send PORT MAP(TXC,reset,W_r,D,TXD,TBE);

	u3:control PORT MAP(RXC,RXD,RESET,LDSR,LDRB,RXEN,SCLK,FE);
	u4:shifter PORT MAP(RXD,LDRB,LDSR,RXEN,TBE,W_r,D,PE);
end;