reg.rpt

本程序是用VHDL语言实现异步通信控制器

Device-Specific Information:                                   d:\zong\reg.rpt
reg

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                                 Logic cells placed in LAB 'B'
        +----------------------- LC24 IRQ
        | +--------------------- LC26 status0
        | | +------------------- LC27 status1
        | | | +----------------- LC25 status2
        | | | | +--------------- LC23 status3
        | | | | | +------------- LC22 status4
        | | | | | | +----------- LC17 status5
        | | | | | | | +--------- LC18 status6
        | | | | | | | | +------- LC19 status7
        | | | | | | | | | +----- LC20 ERXE
        | | | | | | | | | | +--- LC21 ETBE
        | | | | | | | | | | | +- LC29 ERBF
        | | | | | | | | | | | | 
        | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC20 -> * - - - - - - - - - - - | - * | <-- ERXE
LC21 -> * - - - - - - - - - - - | - * | <-- ETBE
LC29 -> * - - - - - - - - - - - | - * | <-- ERBF

Pin
4    -> - * * * * * - - - * * * | - * | <-- A0
18   -> - * * * * * - - - * * * | - * | <-- CS
13   -> - - - - - - - - - - - * | - * | <-- din0
17   -> - - - - - - - - - - * - | - * | <-- din1
16   -> - - - - - - - - - * - - | - * | <-- din2
14   -> - - - - - * - - - - - - | - * | <-- FE
12   -> * - - - * - - - - - - - | - * | <-- OVERFLOW
11   -> * - - * - - - - - - - - | - * | <-- PE
9    -> * * - - - - - - - - - - | - * | <-- RBF
8    -> - * * * * * - - - * * * | - * | <-- RD
7    -> - - - - - - - - - * * * | - * | <-- reset
5    -> * - * - - - - - - - - - | - * | <-- TBE
6    -> - * * * * * - - - * * * | - * | <-- WR


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                   d:\zong\reg.rpt
reg

** EQUATIONS **

A0       : INPUT;
CS       : INPUT;
din0     : INPUT;
din1     : INPUT;
din2     : INPUT;
FE       : INPUT;
OVERFLOW : INPUT;
PE       : INPUT;
RBF      : INPUT;
RD       : INPUT;
reset    : INPUT;
TBE      : INPUT;
WR       : INPUT;

-- Node name is ':30' = 'ERBF' 
-- Equation name is 'ERBF', location is LC029, type is buried.
ERBF     = DFFE( GND $  GND, !reset, !_EQ001, !_EQ002,  VCC);
  _EQ001 =  A0 & !CS & !din0 &  RD &  reset & !WR;
  _EQ002 =  A0 & !CS &  din0 &  RD &  reset & !WR;

-- Node name is ':28' = 'ERXE' 
-- Equation name is 'ERXE', location is LC020, type is buried.
ERXE     = DFFE( GND $  GND, !reset, !_EQ003, !_EQ004,  VCC);
  _EQ003 =  A0 & !CS & !din2 &  RD &  reset & !WR;
  _EQ004 =  A0 & !CS &  din2 &  RD &  reset & !WR;

-- Node name is ':29' = 'ETBE' 
-- Equation name is 'ETBE', location is LC021, type is buried.
ETBE     = DFFE( GND $  GND, !reset, !_EQ005, !_EQ006,  VCC);
  _EQ005 =  A0 & !CS & !din1 &  RD &  reset & !WR;
  _EQ006 =  A0 & !CS &  din1 &  RD &  reset & !WR;

-- Node name is 'IRQ' 
-- Equation name is 'IRQ', location is LC024, type is output.
 IRQ     = LCELL( _EQ007 $  GND);
  _EQ007 =  ERXE &  PE
         #  ERXE &  OVERFLOW
         #  ETBE &  TBE
         #  ERBF &  RBF;

-- Node name is 'status0' 
-- Equation name is 'status0', location is LC026, type is output.
 status0 = LCELL( _EQ008 $  GND);
  _EQ008 =  A0 & !CS &  RBF & !RD &  WR;

-- Node name is 'status1' 
-- Equation name is 'status1', location is LC027, type is output.
 status1 = LCELL( _EQ009 $  GND);
  _EQ009 =  A0 & !CS & !RD &  TBE &  WR;

-- Node name is 'status2' 
-- Equation name is 'status2', location is LC025, type is output.
 status2 = LCELL( _EQ010 $  GND);
  _EQ010 =  A0 & !CS &  PE & !RD &  WR;

-- Node name is 'status3' 
-- Equation name is 'status3', location is LC023, type is output.
 status3 = LCELL( _EQ011 $  GND);
  _EQ011 =  A0 & !CS &  OVERFLOW & !RD &  WR;

-- Node name is 'status4' 
-- Equation name is 'status4', location is LC022, type is output.
 status4 = LCELL( _EQ012 $  GND);
  _EQ012 =  A0 & !CS &  FE & !RD &  WR;

-- Node name is 'status5' 
-- Equation name is 'status5', location is LC017, type is output.
 status5 = LCELL( VCC $  VCC);

-- Node name is 'status6' 
-- Equation name is 'status6', location is LC018, type is output.
 status6 = LCELL( VCC $  VCC);

-- Node name is 'status7' 
-- Equation name is 'status7', location is LC019, type is output.
 status7 = LCELL( VCC $  VCC);



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                            d:\zong\reg.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:00


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,591K