📄 communication.rpt
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Project Informationc:\documents and settings\focuson\desktop\zong\communication.rpt
MAX+plus II Compiler Report File
Version 10.1 06/12/2001
Compiled: 09/06/2005 18:39:42
Copyright (C) 1988-2001 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
COMMUNICATION
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
communication
EPM7096LC68-7 8 2 8 66 49 68 %
User Pins: 7 1 8
Project Informationc:\documents and settings\focuson\desktop\zong\communication.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Ignored unnecessary INPUT pin 'A0'
Project Informationc:\documents and settings\focuson\desktop\zong\communication.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'RXC' chosen for auto global Clock
Project Informationc:\documents and settings\focuson\desktop\zong\communication.rpt
** MULTIPLE PIN CONNECTIONS **
For node name '|receiver:u2|shifter:u2|~606~2' (Same as node '~PIN001')
For node name '|receiver:u2|shifter:u2|~606~1' (Same as node '~PIN002')
Connect: {communication@68,communication@13}
Project Informationc:\documents and settings\focuson\desktop\zong\communication.rpt
** FILE HIERARCHY **
|send:u1|
|send:u1|lpm_add_sub:108|
|send:u1|lpm_add_sub:108|addcore:adder|
|send:u1|lpm_add_sub:108|addcore:adder|addcore:adder0|
|send:u1|lpm_add_sub:108|altshift:result_ext_latency_ffs|
|send:u1|lpm_add_sub:108|altshift:carry_ext_latency_ffs|
|send:u1|lpm_add_sub:108|altshift:oflow_ext_latency_ffs|
|send:u1|lpm_add_sub:341|
|send:u1|lpm_add_sub:341|addcore:adder|
|send:u1|lpm_add_sub:341|addcore:adder|addcore:adder0|
|send:u1|lpm_add_sub:341|altshift:result_ext_latency_ffs|
|send:u1|lpm_add_sub:341|altshift:carry_ext_latency_ffs|
|send:u1|lpm_add_sub:341|altshift:oflow_ext_latency_ffs|
|receiver:u2|
|receiver:u2|control:u1|
|receiver:u2|control:u1|lpm_add_sub:103|
|receiver:u2|control:u1|lpm_add_sub:103|addcore:adder|
|receiver:u2|control:u1|lpm_add_sub:103|addcore:adder|addcore:adder0|
|receiver:u2|control:u1|lpm_add_sub:103|altshift:result_ext_latency_ffs|
|receiver:u2|control:u1|lpm_add_sub:103|altshift:carry_ext_latency_ffs|
|receiver:u2|control:u1|lpm_add_sub:103|altshift:oflow_ext_latency_ffs|
|receiver:u2|control:u1|lpm_add_sub:652|
|receiver:u2|control:u1|lpm_add_sub:652|addcore:adder|
|receiver:u2|control:u1|lpm_add_sub:652|addcore:adder|addcore:adder0|
|receiver:u2|control:u1|lpm_add_sub:652|altshift:result_ext_latency_ffs|
|receiver:u2|control:u1|lpm_add_sub:652|altshift:carry_ext_latency_ffs|
|receiver:u2|control:u1|lpm_add_sub:652|altshift:oflow_ext_latency_ffs|
|receiver:u2|control:u1|lpm_add_sub:846|
|receiver:u2|control:u1|lpm_add_sub:846|addcore:adder|
|receiver:u2|control:u1|lpm_add_sub:846|addcore:adder|addcore:adder0|
|receiver:u2|control:u1|lpm_add_sub:846|altshift:result_ext_latency_ffs|
|receiver:u2|control:u1|lpm_add_sub:846|altshift:carry_ext_latency_ffs|
|receiver:u2|control:u1|lpm_add_sub:846|altshift:oflow_ext_latency_ffs|
|receiver:u2|control:u1|lpm_add_sub:903|
|receiver:u2|control:u1|lpm_add_sub:903|addcore:adder|
|receiver:u2|control:u1|lpm_add_sub:903|addcore:adder|addcore:adder0|
|receiver:u2|control:u1|lpm_add_sub:903|altshift:result_ext_latency_ffs|
|receiver:u2|control:u1|lpm_add_sub:903|altshift:carry_ext_latency_ffs|
|receiver:u2|control:u1|lpm_add_sub:903|altshift:oflow_ext_latency_ffs|
|receiver:u2|control:u1|lpm_add_sub:1377|
|receiver:u2|control:u1|lpm_add_sub:1377|addcore:adder|
|receiver:u2|control:u1|lpm_add_sub:1377|addcore:adder|addcore:adder0|
|receiver:u2|control:u1|lpm_add_sub:1377|altshift:result_ext_latency_ffs|
|receiver:u2|control:u1|lpm_add_sub:1377|altshift:carry_ext_latency_ffs|
|receiver:u2|control:u1|lpm_add_sub:1377|altshift:oflow_ext_latency_ffs|
|receiver:u2|shifter:u2|
Device-Specific Information:c:\documents and settings\focuson\desktop\zong\communication.rpt
communication
***** Logic for device 'communication' compiled without errors.
Device: EPM7096LC68-7
Device Options:
Turbo Bit = ON
Security Bit = OFF
MultiVolt I/O = OFF
R R R R R R
E E ~ E E E E
S S V P S S S S
E E C I E E V E E
R R C N R R C R R
V G V T I G G 0 R G V V C V V
E R C N E X N N N 0 X N E E I E E
D D S D D C T D D 1 C D D D O D D
-----------------------------------------------------_
/ 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 |
RXD | 10 60 | RESERVED
VCCIO | 11 59 | RESERVED
reset | 12 58 | GND
~PIN002 | 13 57 | RESERVED
RESERVED | 14 56 | RESERVED
RESERVED | 15 55 | RESERVED
GND | 16 54 | RESERVED
RESERVED | 17 53 | VCCIO
RESERVED | 18 EPM7096LC68-7 52 | RESERVED
RESERVED | 19 51 | RESERVED
RESERVED | 20 50 | RESERVED
VCCIO | 21 49 | RESERVED
RESERVED | 22 48 | GND
WR | 23 47 | D2
RESERVED | 24 46 | D3
RESERVED | 25 45 | RESERVED
GND | 26 44 | RESERVED
|_ 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 _|
------------------------------------------------------
D D D D V D D G V R T G R R R R V
0 1 7 4 C 5 6 N C E X N E E E E C
C D C S D D S S S S C
I I E E E E E I
O N R R R R R O
T V V V V V
E E E E E
D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information:c:\documents and settings\focuson\desktop\zong\communication.rpt
communication
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 5/16( 31%) 6/ 8( 75%) 11/16( 68%) 17/36( 47%)
B: LC17 - LC32 2/16( 12%) 1/ 8( 12%) 16/16(100%) 13/36( 36%)
C: LC33 - LC48 11/16( 68%) 6/ 8( 75%) 16/16(100%) 24/36( 66%)
D: LC49 - LC64 16/16(100%) 1/ 8( 12%) 16/16(100%) 21/36( 58%)
E: LC65 - LC80 16/16(100%) 2/ 8( 25%) 3/16( 18%) 21/36( 58%)
F: LC81 - LC96 16/16(100%) 0/ 8( 0%) 2/16( 12%) 20/36( 55%)
Total dedicated input pins used: 2/4 ( 50%)
Total I/O pins used: 16/48 ( 33%)
Total logic cells used: 66/96 ( 68%)
Total shareable expanders used: 49/96 ( 51%)
Total Turbo logic cells used: 66/96 ( 68%)
Total shareable expanders not available (n/a): 15/96 ( 15%)
Average fan-in: 7.28
Total fan-in: 481
Total input pins required: 8
Total output pins required: 2
Total bidirectional pins required: 8
Total logic cells required: 66
Total flipflops required: 47
Total product terms required: 256
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 48
Synthesized logic cells: 5/ 96 ( 5%)
Device-Specific Information:c:\documents and settings\focuson\desktop\zong\communication.rpt
communication
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
7 (12) (A) INPUT 0 0 0 0 0 0 1 CS
27 43 C BIDIR 0 0 0 0 4 0 1 D0
28 41 C BIDIR 0 0 0 0 4 0 1 D1
47 67 E BIDIR 0 0 0 0 4 0 1 D2
46 65 E BIDIR 0 0 0 0 4 0 1 D3
30 37 C BIDIR 0 0 0 0 4 0 1 D4
32 35 C BIDIR 0 0 0 0 4 0 1 D5
33 33 C BIDIR 0 0 0 0 4 0 1 D6
29 40 C BIDIR 0 0 0 0 4 0 1 D7
68 - - INPUT G s 0 0 0 0 0 0 0 ~PIN001
8 (9) (A) INPUT 0 0 0 0 0 0 1 RD
12 (4) (A) INPUT 0 0 0 0 0 1 38 reset
67 - - INPUT G 0 0 0 0 0 0 0 RXC
10 (6) (A) INPUT 0 0 0 0 0 0 11 RXD
4 (16) (A) INPUT 0 0 0 0 0 0 6 TXC
23 (17) (B) INPUT 0 0 0 0 0 0 1 WR
Code:
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