📄 selection.vhd
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity selection is
port(CS,A0,RD,WR:IN STD_LOGIC;
Rx_buf:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
status:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
Tx_buf:OUT STD_LOGIC_vector(7 DOWNTO 0);
D:INOUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END;
ARCHITECTURE behavior of selection is
begin
process
begin
IF (CS='0' AND RD='0' AND WR='1') THEN
IF A0='0' THEN
D<=Rx_buf;
ELSE
D<=status;
END IF;
ELSIF CS='0' AND RD='1' AND WR='0' THEN
TX_buf<=D;D<="ZZZZZZZZ";
ELSE D<="ZZZZZZZZ";
end if;
end process;
end;
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