taps.v

关于Altera公司FPGA编程的一些常用实例代码.

// WARNING: Do NOT edit the input and output ports in this file in a text
// editor if you plan to continue editing the block that represents it in
// the Block Editor! File corruption is VERY likely to occur.

// Copyright (C) 1991-2004 Altera Corporation
// Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
// support information,  device programming or simulation file,  and any other
// associated  documentation or information  provided by  Altera  or a partner
// under  Altera's   Megafunction   Partnership   Program  may  be  used  only
// to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
// other  use  of such  megafunction  design,  netlist,  support  information,
// device programming or simulation file,  or any other  related documentation
// or information  is prohibited  for  any  other purpose,  including, but not
// limited to  modification,  reverse engineering,  de-compiling, or use  with
// any other  silicon devices,  unless such use is  explicitly  licensed under
// a separate agreement with  Altera  or a megafunction partner.  Title to the
// intellectual property,  including patents,  copyrights,  trademarks,  trade
// secrets,  or maskworks,  embodied in any such megafunction design, netlist,
// support  information,  device programming or simulation file,  or any other
// related documentation or information provided by  Altera  or a megafunction
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// Generated by Quartus II Version 4.0 (Build Build 184 12/18/2003)
// Created on Mon Jan 05 13:42:39 2004

//  Module Declaration
module taps
(
	// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!	
	clk, newt, reset, d, sel, x, xn, xn_1, xn_2, xn_3
	// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
	// Port Declaration
	// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	input clk, newt, reset;
	input [1:0] sel;
	input [7:0] d;
	output [7:0] x, xn, xn_1, xn_2, xn_3;
	// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!

	// Wire Declaration
	reg [7:0] x, xn, xn_1, xn_2, xn_3;

// Register element
always @(posedge clk or posedge reset)
begin
if (reset)
	begin
		xn = 0;
		xn_1 = 0;
		xn_2 = 0;
		xn_3 = 0;
	end
else if (newt)
	begin
		xn_3 = xn_2;
		xn_2 = xn_1;
		xn_1 = xn;
		xn = d;
	end
end

// Mux element

always @(sel or xn or xn_1 or xn_2 or xn_3)
case (sel)
2'b 00: x = xn;
2'b 01: x = xn_1;
2'b 10: x = xn_2;
2'b 11: x = xn_3;
default: x = 8'b X;
endcase

endmodule