📄 chiptrip.rpt
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LC30 -> * * * * * * * * - - - - - - - - | * * | <-- |auto_max:1|q2
LC23 -> - - - - * * * * - - - - - - - - | - * | <-- ticket0
LC17 -> - - - - - * * * - - - - - - - - | - * | <-- ticket1
LC29 -> - - - - - - * * - - - - - - - - | - * | <-- ticket2
LC25 -> - - - - - - - - * * * * * * * * | - * | <-- time0
LC24 -> - - - - - - - - - * * * * * * * | - * | <-- time1
LC22 -> - - - - - - - - - - * * * * * * | - * | <-- time2
LC21 -> - - - - - - - - - - - * * * * * | - * | <-- time3
LC20 -> - - - - - - - - - - - - * * * * | - * | <-- time4
LC19 -> - - - - - - - - - - - - - * * * | - * | <-- time5
LC18 -> - - - - - - - - - - - - - - * * | - * | <-- time6
Pin
4 -> * * * * * * * * - - - - - - - - | * * | <-- accel
43 -> - - - - - - - - - - - - - - - - | - - | <-- clock
7 -> * * * * * * * * - - - - - - - - | * * | <-- dir0
6 -> * * * * * * * * - - - - - - - - | * * | <-- dir1
8 -> - - - - - - - - * * * * * * * * | - * | <-- enable
5 -> * * - * - - - - - - - - - - - - | * * | <-- reset
LC8 -> - - - - * * * * - - - - - - - - | - * | <-- |speed_ch:2|:33
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\max2work\tutorial\chiptrip.rpt
chiptrip
** EQUATIONS **
accel : INPUT;
clock : INPUT;
dir0 : INPUT;
dir1 : INPUT;
enable : INPUT;
reset : INPUT;
-- Node name is 'at_altera'
-- Equation name is 'at_altera', location is LC006, type is output.
at_altera = LCELL( _EQ001 $ GND);
_EQ001 = _LC030 & !_LC031 & !_LC032;
-- Node name is 'ticket0' = '|tick_cnt:10|8count:8|p8count:sub|QA'
-- Equation name is 'ticket0', type is output
ticket0 = TFFE( _EQ002, GLOBAL( clock), VCC, VCC, VCC);
_EQ002 = accel & !dir0 & dir1 & !_LC031 & _LC032
# accel & dir0 & !dir1 & !_LC030 & !_LC031
# _LC008;
-- Node name is 'ticket1' = '|tick_cnt:10|8count:8|p8count:sub|QB'
-- Equation name is 'ticket1', type is output
ticket1 = TFFE( _EQ003, GLOBAL( clock), VCC, VCC, VCC);
_EQ003 = accel & !dir0 & dir1 & !_LC031 & _LC032 & ticket0
# accel & dir0 & !dir1 & !_LC030 & !_LC031 & ticket0
# _LC008 & ticket0;
-- Node name is 'ticket2' = '|tick_cnt:10|8count:8|p8count:sub|QC'
-- Equation name is 'ticket2', type is output
ticket2 = TFFE( _EQ004, GLOBAL( clock), VCC, VCC, VCC);
_EQ004 = accel & !dir0 & dir1 & !_LC031 & _LC032 & ticket0 & ticket1
# accel & dir0 & !dir1 & !_LC030 & !_LC031 & ticket0 & ticket1
# _LC008 & ticket0 & ticket1;
-- Node name is 'ticket3' = '|tick_cnt:10|8count:8|p8count:sub|QD'
-- Equation name is 'ticket3', type is output
ticket3 = TFFE( _EQ005, GLOBAL( clock), VCC, VCC, VCC);
_EQ005 = accel & !dir0 & dir1 & !_LC031 & _LC032 & ticket0 & ticket1 &
ticket2
# accel & dir0 & !dir1 & !_LC030 & !_LC031 & ticket0 & ticket1 &
ticket2
# _LC008 & ticket0 & ticket1 & ticket2;
-- Node name is 'time0' = '|time_cnt:4|count0' from file "time_cnt.tdf" line 7, column 7
-- Equation name is 'time0', type is output
time0 = TFFE( enable, GLOBAL( clock), VCC, VCC, VCC);
-- Node name is 'time1' = '|time_cnt:4|count1' from file "time_cnt.tdf" line 7, column 7
-- Equation name is 'time1', type is output
time1 = TFFE( _EQ006, GLOBAL( clock), VCC, VCC, VCC);
_EQ006 = enable & time0;
-- Node name is 'time2' = '|time_cnt:4|count2' from file "time_cnt.tdf" line 7, column 7
-- Equation name is 'time2', type is output
time2 = TFFE( _EQ007, GLOBAL( clock), VCC, VCC, VCC);
_EQ007 = enable & time0 & time1;
-- Node name is 'time3' = '|time_cnt:4|count3' from file "time_cnt.tdf" line 7, column 7
-- Equation name is 'time3', type is output
time3 = TFFE( _EQ008, GLOBAL( clock), VCC, VCC, VCC);
_EQ008 = enable & time0 & time1 & time2;
-- Node name is 'time4' = '|time_cnt:4|count4' from file "time_cnt.tdf" line 7, column 7
-- Equation name is 'time4', type is output
time4 = TFFE( _EQ009, GLOBAL( clock), VCC, VCC, VCC);
_EQ009 = enable & time0 & time1 & time2 & time3;
-- Node name is 'time5' = '|time_cnt:4|count5' from file "time_cnt.tdf" line 7, column 7
-- Equation name is 'time5', type is output
time5 = TFFE( _EQ010, GLOBAL( clock), VCC, VCC, VCC);
_EQ010 = enable & time0 & time1 & time2 & time3 & time4;
-- Node name is 'time6' = '|time_cnt:4|count6' from file "time_cnt.tdf" line 7, column 7
-- Equation name is 'time6', type is output
time6 = TFFE( _EQ011, GLOBAL( clock), VCC, VCC, VCC);
_EQ011 = enable & time0 & time1 & time2 & time3 & time4 & time5;
-- Node name is 'time7' = '|time_cnt:4|count7' from file "time_cnt.tdf" line 7, column 7
-- Equation name is 'time7', type is output
time7 = TFFE( _EQ012, GLOBAL( clock), VCC, VCC, VCC);
_EQ012 = enable & time0 & time1 & time2 & time3 & time4 & time5 &
time6;
-- Node name is '|auto_max:1|q0' from file "auto_max.tdf" line 13, column 21
-- Equation name is '_LC031', type is buried
_LC031 = DFFE( _EQ013 $ _EQ014, GLOBAL( clock), !reset, VCC, VCC);
_EQ013 = !accel & dir0 & dir1 & _LC030 & _LC031 & _X001 & _X002 &
_X003 & _X004 & _X005
# !dir0 & !dir1 & _LC030 & _LC031 & _LC032 & _X001 & _X002 &
_X003 & _X004 & _X005
# accel & dir1 & !_LC030 & _LC031 & !_LC032 & _X001 & _X002 &
_X003 & _X004 & _X005;
_X001 = EXP( _LC030 & !_LC031 & !_LC032);
_X002 = EXP( dir0 & dir1 & _LC031 & _LC032);
_X003 = EXP( accel & _LC030 & !_LC031);
_X004 = EXP( dir0 & !_LC031);
_X005 = EXP( dir1 & !_LC031);
_EQ014 = _X001 & _X002 & _X003 & _X004 & _X005;
_X001 = EXP( _LC030 & !_LC031 & !_LC032);
_X002 = EXP( dir0 & dir1 & _LC031 & _LC032);
_X003 = EXP( accel & _LC030 & !_LC031);
_X004 = EXP( dir0 & !_LC031);
_X005 = EXP( dir1 & !_LC031);
-- Node name is '|auto_max:1|q1' from file "auto_max.tdf" line 13, column 18
-- Equation name is '_LC032', type is buried
_LC032 = DFFE( _EQ015 $ _EQ016, GLOBAL( clock), !reset, VCC, VCC);
_EQ015 = !dir0 & !dir1 & _LC031 & _LC032 & _X001 & _X006 & _X007 &
_X008 & _X009
# !dir0 & dir1 & !_LC030 & _LC032 & _X001 & _X006 & _X007 &
_X008 & _X009
# !dir1 & !_LC030 & _LC031 & !_LC032 & _X001 & _X006 & _X007 &
_X008 & _X009;
_X001 = EXP( _LC030 & !_LC031 & !_LC032);
_X006 = EXP( accel & !dir0 & _LC032);
_X007 = EXP( dir1 & _LC030 & !_LC032);
_X008 = EXP( dir1 & !_LC031 & !_LC032);
_X009 = EXP(!dir0 & !_LC032);
_EQ016 = _X001 & _X006 & _X007 & _X008 & _X009;
_X001 = EXP( _LC030 & !_LC031 & !_LC032);
_X006 = EXP( accel & !dir0 & _LC032);
_X007 = EXP( dir1 & _LC030 & !_LC032);
_X008 = EXP( dir1 & !_LC031 & !_LC032);
_X009 = EXP(!dir0 & !_LC032);
-- Node name is '|auto_max:1|q2~1' from file "auto_max.tdf" line 13, column 15
-- Equation name is '_LC027', type is buried
-- synthesized logic cell
_LC027 = LCELL( _EQ017 $ GND);
_EQ017 = accel & !_LC030 & _LC031 & !_LC032
# !dir0 & !dir1 & _LC031 & !_LC032
# accel & !dir0 & !_LC030 & !_LC032
# !dir0 & !dir1 & !_LC030 & _LC032
# !accel & dir0 & !_LC030 & !_LC032;
-- Node name is '|auto_max:1|q2' from file "auto_max.tdf" line 13, column 15
-- Equation name is '_LC030', type is buried
_LC030 = DFFE( _EQ018 $ _EQ019, GLOBAL( clock), !reset, VCC, VCC);
_EQ018 = !accel & !dir0 & dir1 & !_LC027 & _LC030 & _LC032 & _X010 &
_X011
# !accel & dir0 & !_LC027 & _LC031 & !_LC032 & _X010 & _X011
# !dir0 & dir1 & !_LC027 & !_LC031 & _LC032 & _X010 & _X011;
_X010 = EXP( dir0 & dir1 & !_LC030);
_X011 = EXP( dir1 & !_LC030 & !_LC031);
_EQ019 = !_LC027 & _X010 & _X011;
_X010 = EXP( dir0 & dir1 & !_LC030);
_X011 = EXP( dir1 & !_LC030 & !_LC031);
-- Node name is '|speed_ch:2|speed~1'
-- Equation name is '_LC016', type is buried
_LC016 = DFFE( _EQ020 $ _EQ021, GLOBAL( clock), !reset, VCC, VCC);
_EQ020 = accel & dir0 & !dir1 & _LC012 & !_LC016 & _LC030 & _LC032 &
_X001 & _X007 & _X008 & _X010 & _X012
# accel & !dir1 & _LC012 & !_LC016 & !_LC030 & _LC031 & !_LC032 &
_X001 & _X007 & _X008 & _X010 & _X012
# accel & !dir0 & !dir1 & _LC012 & !_LC016 & !_LC030 & _LC032 &
_X001 & _X007 & _X008 & _X010 & _X012;
_X001 = EXP( _LC030 & !_LC031 & !_LC032);
_X007 = EXP( dir1 & _LC030 & !_LC032);
_X008 = EXP( dir1 & !_LC031 & !_LC032);
_X010 = EXP( dir0 & dir1 & !_LC030);
_X012 = EXP( dir0 & _LC030 & !_LC031);
_EQ021 = accel & _LC012 & !_LC016 & _X001 & _X007 & _X008 & _X010 &
_X012;
_X001 = EXP( _LC030 & !_LC031 & !_LC032);
_X007 = EXP( dir1 & _LC030 & !_LC032);
_X008 = EXP( dir1 & !_LC031 & !_LC032);
_X010 = EXP( dir0 & dir1 & !_LC030);
_X012 = EXP( dir0 & _LC030 & !_LC031);
-- Node name is '|speed_ch:2|speed~2~1'
-- Equation name is '_LC004', type is buried
-- synthesized logic cell
_LC004 = LCELL( _EQ022 $ GND);
_EQ022 = accel & dir1 & !_LC016 & _LC030 & _LC031 & _LC032
# accel & !dir0 & dir1 & !_LC016 & !_LC030 & _LC031
# accel & !dir1 & !_LC016 & _LC030 & _LC031 & !_LC032
# accel & dir0 & !dir1 & !_LC016 & !_LC030 & _LC032
# accel & !dir1 & !_LC016 & !_LC030 & !_LC031 & !_LC032;
-- Node name is '|speed_ch:2|speed~2'
-- Equation name is '_LC012', type is buried
_LC012 = TFFE(!_EQ023, GLOBAL( clock), !reset, VCC, VCC);
_EQ023 = !_LC004 & _X013 & _X014;
_X013 = EXP( accel & !dir0 & dir1 & !_LC016 & _LC032);
_X014 = EXP( accel & !dir0 & !_LC016 & _LC030 & _LC032);
-- Node name is '|speed_ch:2|:33'
-- Equation name is '_LC008', type is buried
_LC008 = DFFE( _EQ024 $ _EQ025, GLOBAL( clock), VCC, VCC, VCC);
_EQ024 = accel & dir0 & !dir1 & _LC012 & !_LC016 & _LC030 & _LC032 &
_X001 & _X007 & _X008 & _X010 & _X012
# accel & dir0 & _LC012 & !_LC016 & !_LC030 & _LC031 & !_LC032 &
_X001 & _X007 & _X008 & _X010 & _X012
# accel & !dir0 & !dir1 & _LC012 & !_LC016 & !_LC030 & _LC032 &
_X001 & _X007 & _X008 & _X010 & _X012
# accel & !dir0 & !dir1 & _LC012 & !_LC016 & !_LC030 & _LC031 &
_X001 & _X007 & _X008 & _X010 & _X012;
_X001 = EXP( _LC030 & !_LC031 & !_LC032);
_X007 = EXP( dir1 & _LC030 & !_LC032);
_X008 = EXP( dir1 & !_LC031 & !_LC032);
_X010 = EXP( dir0 & dir1 & !_LC030);
_X012 = EXP( dir0 & _LC030 & !_LC031);
_EQ025 = accel & _LC012 & !_LC016 & _X001 & _X007 & _X008 & _X010 &
_X012;
_X001 = EXP( _LC030 & !_LC031 & !_LC032);
_X007 = EXP( dir1 & _LC030 & !_LC032);
_X008 = EXP( dir1 & !_LC031 & !_LC032);
_X010 = EXP( dir0 & dir1 & !_LC030);
_X012 = EXP( dir0 & _LC030 & !_LC031);
-- Shareable expanders that are duplicated in multiple LABs:
-- _X001 occurs in LABs A, B
-- _X007 occurs in LABs A, B
-- _X008 occurs in LABs A, B
-- _X010 occurs in LABs A, B
Project Information d:\max2work\tutorial\chiptrip.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = on
Rules = EPLD Rules
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = on
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:01
Logic Synthesizer 00:00:01
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
Design Doctor 00:00:00
-------------------------- --------
Total Time 00:00:05
Memory Allocated
-----------------
Peak memory allocated during compilation = 2,933K
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