auto_max.tdf

关于Altera公司FPGA编程的一些常用实例代码.

CONSTANT NORTH = B"00";         % Create descriptive name for numbers   %
CONSTANT EAST  = B"01";         % for use elsewhere in file             %
CONSTANT WEST  = B"10";
CONSTANT SOUTH = B"11";
SUBDESIGN auto_max
(
	dir[1..0], accel, clk, reset            : INPUT;        % File inputs   %
	speed_too_fast, at_altera, get_ticket   : OUTPUT;       % File outputs  %
)

VARIABLE
	street_map : MACHINE                    % Create state machine with bits q2,    %
					OF BITS (q2,q1,q0)      % q1 & q0 as outputs of register        %
					WITH STATES (
						yc,                 % Your company                  %
						mpld,               % Marigold Park Lane Drive      %
						epld,               % East Pacific Lane Drive       %
						gdf,                % Great Delta Freeway           %
						cnf,                % Capitol North First           %
						rpt,                % Regal Park Terrace            %
						epm,                % East Pacific Main             %
						altera );           % Your one-stop programmable logic shop %

BEGIN
	street_map.clk          = clk;          % input pin "clk" connects to state machine clk          %
	street_map.reset        = reset;        % input pin "reset" connects to state machine reset		 %
											% File outputs default to GND unless otherwise specified %

	TABLE                                   % Define state transitions %

	% Present                       Next                                              %
	% State     Inputs              State       Outputs                               %

	street_map, dir[1..0], accel => street_map, get_ticket, at_altera, speed_too_fast; 
    % ------------------------------------------------------------------------------- %
    % When street_map is in the state yc, dir[1..0] = 00, and accel = 0, it enters    %
	% the state rpt and outputs 0 for get_ticket, at_altera, and speed_too_fast.      %
	yc,         NORTH,     0     => rpt,        0,          0,         0;
    yc,         EAST,      0     => gdf,        0,          0,         0;
    yc,         NORTH,     1     => mpld,       0,          0,         1;
    yc,         EAST,      1     => cnf,        1,          0,         1;
    gdf,        NORTH,     0     => epld,       0,          0,         0;
    gdf,        WEST,      0     => yc,         0,          0,         0;
    gdf,        WEST,      1     => yc,         1,          0,         1;
    gdf,        EAST,      0     => cnf,        0,          0,         0;
    gdf,        EAST,      1     => cnf,        1,          0,         1;
    gdf,        NORTH,     1     => mpld,       0,          0,         0;
    cnf,        NORTH,     0     => epm,        0,          0,         0;
    cnf,        WEST,      0     => gdf,        0,          0,         0;
    cnf,        NORTH,     1     => altera,     0,          0,         1;
    cnf,        WEST,      1     => yc,         1,          0,         1;
    rpt,        NORTH,     0     => mpld,       0,          0,         0;
    rpt,        NORTH,     1     => mpld,       0,          0,         1;
    rpt,        EAST,      0     => epld,       0,          0,         0;
    rpt,        EAST,      1     => epm,        0,          0,         1;
    rpt,        SOUTH,     0     => yc,         0,          0,         0;
    epld,       NORTH,     X     => mpld,       0,          0,         0;
    epld,       WEST,      0     => rpt,        0,          0,         0;
    epld,       WEST,      1     => rpt,        0,          0,         1;
    epld,       SOUTH,     X     => gdf,        0,          0,         0;
    epld,       EAST,      0     => epm,        0,          0,         0;
    epld,       EAST,      1     => epm,        0,          0,         1;
    epm,        NORTH,     0     => altera,     0,          0,         0;
    epm,        NORTH,     1     => altera,     0,          0,         1;
    epm,        SOUTH,     0     => cnf,        0,          0,         0;
    epm,        SOUTH,     1     => cnf,        0,          0,         1;
    epm,        WEST,      0     => epld,       0,          0,         0;
    epm,        WEST,      1     => rpt,        0,          0,         1;
    mpld,       WEST,      0     => rpt,        0,          0,         0;
    mpld,       SOUTH,     0     => epld,       0,          0,         0;
    mpld,       WEST,      1     => yc,         0,          0,         1;
    mpld,       SOUTH,     1     => gdf,        0,          0,         0;
    altera,     X,         X     => altera,     0,          1,         0;
	
	END TABLE;
	
END;