speed_ch.tdf

关于Altera公司FPGA编程的一些常用实例代码.

SUBDESIGN speed_ch
(
	Accel_in, reset, clk	: INPUT;	% File inputs	%
	get_ticket				: OUTPUT	% File output	%
	% File outputs default to GND unless otherwise specified	%
)

VARIABLE
	speed	:	MACHINE				% Create state machine called	%
				OF BITS (q1,qo)		% speed with bits q1 & q0		%
				WITH STATES (	

	legal,			% You are driving at a legal speed		%
	warning,		% Police are giving you a warning!		%
	ticket			% Police are giving you a ticket!		%

	);

	gt	:	dff;	% Define flip-flop called gt %
	spd_out	:	node;	% Define node called spd_out %

BEGIN
	speed.clk	= clk;		% Connect clock input of speed to INPUT clk		%
	speed.reset	= reset;	% Connect reset input of speed to INPUT reset	%
	gt.clk		= clk;		% Connect clock input of gt to INPUT clk		%
	gt.d		= spd_out;	% Connect d input of gt to node spd_out			%
	get_ticket	= gt.q;		% Connect OUTPUT get_ticket to q output of gt	%
	
	CASE speed IS
           
	WHEN legal =>               
      
		IF accel_in THEN
			speed = warning;

		ELSE
			speed = legal;

		END IF;

	WHEN warning =>

		IF accel_in THEN
			speed = ticket;
			spd_out = VCC;

		ELSE
			speed = warning;

		END IF;

	WHEN ticket =>
		
		spd_out = GND;
		speed = legal;

END CASE;

END;