acc.v

关于Altera公司FPGA编程的一些常用实例代码.

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// Copyright (C) 1991-2004 Altera Corporation
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// support information,  device programming or simulation file,  and any other
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// Generated by Quartus II Version 4.0 (Build Build 184 12/18/2003)
// Created on Mon Jan 05 13:42:39 2004

//  Module Declaration
module acc
(
	// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
	xh, clk, first, yn
	// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration

	// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	input [10:0] xh;
	input clk;
	input first;
	output [7:0] yn;
	// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!

    reg [7:0]yn;
reg [11:0] ynm, inter, result, a_in;

// Describe Multiplexer

always @(first or result)
begin
	case (first)
		1'b 0: ynm = result;
		1'b 1: ynm = 12'b000000000000;
	endcase
end
	
always @(posedge clk)
begin
	result = inter;
end

always @(xh)
begin
	a_in[10:0] = (xh);
	a_in[11] = 0;
end

always @(result)
	begin 
		yn[7:0] = result[11:4];
	end

accum inst_1(.dataa(a_in), .datab(ynm), .result(inter));

endmodule