cnt5.rpt
来自「步进的控制电机控制 c++环境下开发」· RPT 代码 · 共 497 行 · 第 1/2 页
RPT
497 行
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\step_1k30\cnt5.rpt
cnt5
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - B 04 AND2 0 2 0 3 |LPM_ADD_SUB:27|addcore:adder|:59
- 2 - B 04 DFFE + 0 3 1 0 CQI4 (:7)
- 5 - B 04 DFFE + 0 2 1 1 CQI3 (:8)
- 1 - B 04 DFFE + 0 1 1 2 CQI2 (:9)
- 4 - B 04 DFFE + 0 1 1 1 CQI1 (:10)
- 3 - B 04 DFFE + 0 0 1 2 CQI0 (:11)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\step_1k30\cnt5.rpt
cnt5
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 3/ 96( 3%) 2/ 48( 4%) 0/ 48( 0%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\step_1k30\cnt5.rpt
cnt5
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 5 CLK
Device-Specific Information: d:\step_1k30\cnt5.rpt
cnt5
** EQUATIONS **
CLK : INPUT;
-- Node name is ':11' = 'CQI0'
-- Equation name is 'CQI0', location is LC3_B4, type is buried.
CQI0 = DFFE(!CQI0, GLOBAL( CLK), VCC, VCC, VCC);
-- Node name is ':10' = 'CQI1'
-- Equation name is 'CQI1', location is LC4_B4, type is buried.
CQI1 = DFFE( _EQ001, GLOBAL( CLK), VCC, VCC, VCC);
_EQ001 = !CQI0 & CQI1
# CQI0 & !CQI1;
-- Node name is ':9' = 'CQI2'
-- Equation name is 'CQI2', location is LC1_B4, type is buried.
CQI2 = DFFE( _EQ002, GLOBAL( CLK), VCC, VCC, VCC);
_EQ002 = CQI2 & !_LC6_B4
# !CQI2 & _LC6_B4;
-- Node name is ':8' = 'CQI3'
-- Equation name is 'CQI3', location is LC5_B4, type is buried.
CQI3 = DFFE( _EQ003, GLOBAL( CLK), VCC, VCC, VCC);
_EQ003 = !CQI2 & CQI3
# CQI3 & !_LC6_B4
# CQI2 & !CQI3 & _LC6_B4;
-- Node name is ':7' = 'CQI4'
-- Equation name is 'CQI4', location is LC2_B4, type is buried.
CQI4 = DFFE( _EQ004, GLOBAL( CLK), VCC, VCC, VCC);
_EQ004 = !CQI2 & CQI4
# CQI4 & !_LC6_B4
# !CQI3 & CQI4
# CQI2 & CQI3 & !CQI4 & _LC6_B4;
-- Node name is 'CQ0'
-- Equation name is 'CQ0', type is output
CQ0 = CQI0;
-- Node name is 'CQ1'
-- Equation name is 'CQ1', type is output
CQ1 = CQI1;
-- Node name is 'CQ2'
-- Equation name is 'CQ2', type is output
CQ2 = CQI2;
-- Node name is 'CQ3'
-- Equation name is 'CQ3', type is output
CQ3 = CQI3;
-- Node name is 'CQ4'
-- Equation name is 'CQ4', type is output
CQ4 = CQI4;
-- Node name is '|LPM_ADD_SUB:27|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_B4', type is buried
_LC6_B4 = LCELL( _EQ005);
_EQ005 = CQI0 & CQI1;
Project Information d:\step_1k30\cnt5.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 18,512K
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