step_a.fit.qmsg

来自「步进的控制电机控制 c++环境下开发」· QMSG 代码 · 共 51 行 · 第 1/2 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 23 11:36:36 2005 " "Info: Processing started: Sat Apr 23 11:36:36 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --import_settings_files=off --export_settings_files=off step_a -c step_a " "Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off step_a -c step_a" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "step_a EP1C6Q240C8 " "Info: Selected device EP1C6Q240C8 for design step_a" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Info: Fitter is performing a Standard Fit compilation -- maximum Fitter effort will be used to optimize design performance" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C12Q240C8 " "Info: Device EP1C12Q240C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "5 37 " "Info: No exact pin location assignment(s) for 5 pins of 37 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "COUT " "Info: Pin COUT not assigned to an exact location on the device" {  } { { "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/step_a.bdf" "" "" { Schematic "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/step_a.bdf" { { 752 672 848 768 "COUT" "" } } } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "COUT" } } } } { "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/db/step_a_cmp.qrpt" "" "" { Report "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/db/step_a.quartus_db" { Floorplan "" "" "" { COUT } "NODE_NAME" } } } { "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/step_a.fld" "" "" { Floorplan "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/step_a.fld" "" "" { COUT } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "altera_reserved_tdo " "Info: Pin altera_reserved_tdo not assigned to an exact location on the device" {  } { { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "altera_reserved_tdo" } } } } { "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/db/step_a_cmp.qrpt" "" "" { Report "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/db/step_a.quartus_db" { Floorplan "" "" "" { altera_reserved_tdo } "NODE_NAME" } } } { "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/step_a.fld" "" "" { Floorplan "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/step_a.fld" "" "" { altera_reserved_tdo } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "altera_reserved_tms " "Info: Pin altera_reserved_tms not assigned to an exact location on the device" {  } { { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "altera_reserved_tms" } } } } { "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/db/step_a_cmp.qrpt" "" "" { Report "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/db/step_a.quartus_db" { Floorplan "" "" "" { altera_reserved_tms } "NODE_NAME" } } } { "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/step_a.fld" "" "" { Floorplan "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/step_a.fld" "" "" { altera_reserved_tms } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "altera_reserved_tck " "Info: Pin altera_reserved_tck not assigned to an exact location on the device" {  } { { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "altera_reserved_tck" } } } } { "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/db/step_a_cmp.qrpt" "" "" { Report "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/db/step_a.quartus_db" { Floorplan "" "" "" { altera_reserved_tck } "NODE_NAME" } } } { "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/step_a.fld" "" "" { Floorplan "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/step_a.fld" "" "" { altera_reserved_tck } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "altera_reserved_tdi " "Info: Pin altera_reserved_tdi not assigned to an exact location on the device" {  } { { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "altera_reserved_tdi" } } } } { "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/db/step_a_cmp.qrpt" "" "" { Report "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/db/step_a.quartus_db" { Floorplan "" "" "" { altera_reserved_tdi } "NODE_NAME" } } } { "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/step_a.fld" "" "" { Floorplan "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/step_a.fld" "" "" { altera_reserved_tdi } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "ITAN_TDC_USER_OPTIMIZATION_GOALS" "" "Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "altera_internal_jtag~TCKUTAP Global clock " "Info: Automatically promoted signal altera_internal_jtag~TCKUTAP to use Global clock" {  } { { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TDO" } } } } { "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/db/step_a_cmp.qrpt" "" "" { Report "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/db/step_a.quartus_db" { Floorplan "" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } } } { "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/step_a.fld" "" "" { Floorplan "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/step_a.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk0 Global clock " "Info: Automatically promoted signal clk0 to use Global clock" {  } { { "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/step_a.bdf" "" "" { Schematic "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/step_a.bdf" { { 320 176 344 336 "clk0" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "clk0 " "Info: Pin clk0 drives global clock, but is not placed in a dedicated clock pin position" {  } { { "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/step_a.bdf" "" "" { Schematic "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/step_a.bdf" { { 320 176 344 336 "clk0" "" } } } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "clk0" } } } } { "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/db/step_a_cmp.qrpt" "" "" { Report "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/db/step_a.quartus_db" { Floorplan "" "" "" { clk0 } "NODE_NAME" } } } { "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/step_a.fld" "" "" { Floorplan "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/step_a.fld" "" "" { clk0 } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "CNTT Global clock " "Info: Automatically promoted signal CNTT to use Global clock" {  } { { "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/step_a.bdf" "" "" { Schematic "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/step_a.bdf" { { 840 256 424 856 "CNTT" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "CNTT " "Info: Pin CNTT drives global clock, but is not placed in a dedicated clock pin position" {  } { { "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/step_a.bdf" "" "" { Schematic "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/step_a.bdf" { { 840 256 424 856 "CNTT" "" } } } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "CNTT" } } } } { "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/db/step_a_cmp.qrpt" "" "" { Report "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/db/step_a.quartus_db" { Floorplan "" "" "" { CNTT } "NODE_NAME" } } } { "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/step_a.fld" "" "" { Floorplan "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/step_a.fld" "" "" { CNTT } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "FREQTEST:121\|TESTCTL:U1\|Div2CLK Global clock " "Info: Automatically promoted some destinations of signal FREQTEST:121\|TESTCTL:U1\|Div2CLK to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FREQTEST:121\|CNT:U3\|lpm_counter:lpm_counter_component\|cntr_8f8:auto_generated\|counter_cella15 " "Info: Destination FREQTEST:121\|CNT:U3\|lpm_counter:lpm_counter_component\|cntr_8f8:auto_generated\|counter_cella15 may be non-global or may not use global clock" {  } { { "D:/step_1C3/db/cntr_8f8.tdf" "" "" { Text "D:/step_1C3/db/cntr_8f8.tdf" 180 8 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FREQTEST:121\|TESTCTL:U1\|Div2CLK " "Info: Destination FREQTEST:121\|TESTCTL:U1\|Div2CLK may be non-global or may not use global clock" {  } { { "D:/step_1C3/testctl.vhd" "" "" { Text "D:/step_1C3/testctl.vhd" 15 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FREQTEST:121\|CNT:U3\|lpm_counter:lpm_counter_component\|cntr_8f8:auto_generated\|counter_cella14 " "Info: Destination FREQTEST:121\|CNT:U3\|lpm_counter:lpm_counter_component\|cntr_8f8:auto_generated\|counter_cella14 may be non-global or may not use global clock" {  } { { "D:/step_1C3/db/cntr_8f8.tdf" "" "" { Text "D:/step_1C3/db/cntr_8f8.tdf" 180 8 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FREQTEST:121\|CNT:U3\|lpm_counter:lpm_counter_component\|cntr_8f8:auto_generated\|counter_cella13 " "Info: Destination FREQTEST:121\|CNT:U3\|lpm_counter:lpm_counter_component\|cntr_8f8:auto_generated\|counter_cella13 may be non-global or may not use global clock" {  } { { "D:/step_1C3/db/cntr_8f8.tdf" "" "" { Text "D:/step_1C3/db/cntr_8f8.tdf" 180 8 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FREQTEST:121\|CNT:U3\|lpm_counter:lpm_counter_component\|cntr_8f8:auto_generated\|counter_cella12 " "Info: Destination FREQTEST:121\|CNT:U3\|lpm_counter:lpm_counter_component\|cntr_8f8:auto_generated\|counter_cella12 may be non-global or may not use global clock" {  } { { "D:/step_1C3/db/cntr_8f8.tdf" "" "" { Text "D:/step_1C3/db/cntr_8f8.tdf" 180 8 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FREQTEST:121\|CNT:U3\|lpm_counter:lpm_counter_component\|cntr_8f8:auto_generated\|counter_cella11 " "Info: Destination FREQTEST:121\|CNT:U3\|lpm_counter:lpm_counter_component\|cntr_8f8:auto_generated\|counter_cella11 may be non-global or may not use global clock" {  } { { "D:/step_1C3/db/cntr_8f8.tdf" "" "" { Text "D:/step_1C3/db/cntr_8f8.tdf" 180 8 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FREQTEST:121\|CNT:U3\|lpm_counter:lpm_counter_component\|cntr_8f8:auto_generated\|counter_cella10 " "Info: Destination FREQTEST:121\|CNT:U3\|lpm_counter:lpm_counter_component\|cntr_8f8:auto_generated\|counter_cella10 may be non-global or may not use global clock" {  } { { "D:/step_1C3/db/cntr_8f8.tdf" "" "" { Text "D:/step_1C3/db/cntr_8f8.tdf" 180 8 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FREQTEST:121\|CNT:U3\|lpm_counter:lpm_counter_component\|cntr_8f8:auto_generated\|counter_cella9 " "Info: Destination FREQTEST:121\|CNT:U3\|lpm_counter:lpm_counter_component\|cntr_8f8:auto_generated\|counter_cella9 may be non-global or may not use global clock" {  } { { "D:/step_1C3/db/cntr_8f8.tdf" "" "" { Text "D:/step_1C3/db/cntr_8f8.tdf" 180 8 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FREQTEST:121\|CNT:U3\|lpm_counter:lpm_counter_component\|cntr_8f8:auto_generated\|counter_cella8 " "Info: Destination FREQTEST:121\|CNT:U3\|lpm_counter:lpm_counter_component\|cntr_8f8:auto_generated\|counter_cella8 may be non-global or may not use global clock" {  } { { "D:/step_1C3/db/cntr_8f8.tdf" "" "" { Text "D:/step_1C3/db/cntr_8f8.tdf" 180 8 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "FREQTEST:121\|CNT:U3\|lpm_counter:lpm_counter_component\|cntr_8f8:auto_generated\|counter_cella7 " "Info: Destination FREQTEST:121\|CNT:U3\|lpm_counter:lpm_counter_component\|cntr_8f8:auto_generated\|counter_cella7 may be non-global or may not use global clock" {  } { { "D:/step_1C3/db/cntr_8f8.tdf" "" "" { Text "D:/step_1C3/db/cntr_8f8.tdf" 180 8 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_LIMITED_TO_SUB" "10 " "Info: Limited to 10 non-global destinations" {  } {  } 0}  } { { "D:/step_1C3/testctl.vhd" "" "" { Text "D:/step_1C3/testctl.vhd" 15 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk5 Global clock " "Info: Automatically promoted signal clk5 to use Global clock" {  } { { "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/step_a.bdf" "" "" { Schematic "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/step_a.bdf" { { 280 184 352 296 "clk5" "" } { 592 80 128 608 "CLK5" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "clk5 " "Info: Pin clk5 drives global clock, but is not placed in a dedicated clock pin position" {  } { { "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/step_a.bdf" "" "" { Schematic "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/step_a.bdf" { { 280 184 352 296 "clk5" "" } { 592 80 128 608 "CLK5" "" } } } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "clk5" } } } } { "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/db/step_a_cmp.qrpt" "" "" { Report "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/db/step_a.quartus_db" { Floorplan "" "" "" { clk5 } "NODE_NAME" } } } { "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/step_a.fld" "" "" { Floorplan "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/step_a.fld" "" "" { clk5 } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "D_STP Global clock " "Info: Automatically promoted signal D_STP to use Global clock" {  } { { "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/step_a.bdf" "" "" { Schematic "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/step_a.bdf" { { 552 168 336 568 "D_STP" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "D_STP " "Info: Pin D_STP drives global clock, but is not placed in a dedicated clock pin position" {  } { { "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/step_a.bdf" "" "" { Schematic "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/step_a.bdf" { { 552 168 336 568 "D_STP" "" } } } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "D_STP" } } } } { "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/db/step_a_cmp.qrpt" "" "" { Report "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/db/step_a_cmp.qrpt" Compiler "step_a" "UNKNOWN" "V1" "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/db/step_a.quartus_db" { Floorplan "" "" "" { D_STP } "NODE_NAME" } } } { "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/step_a.fld" "" "" { Floorplan "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/step_a.fld" "" "" { D_STP } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "sld_hub:sld_hub_inst\|CLEAR_SIGNAL~0 Global clock " "Info: Automatically promoted signal sld_hub:sld_hub_inst\|CLEAR_SIGNAL~0 to use Global clock" {  } { { "d:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "d:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 307 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "rom3:inst\|altsyncram:altsyncram_component\|altsyncram_0fs:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:name_gen:info_rom_sr\|clear_signal Global clock " "Info: Automatically promoted signal rom3:inst\|altsyncram:altsyncram_component\|altsyncram_0fs:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:name_gen:info_rom_sr\|clear_signal to use Global clock" {  } { { "d:/altera/quartus41/libraries/megafunctions/sld_rom_sr.vhd" "" "" { Text "d:/altera/quartus41/libraries/megafunctions/sld_rom_sr.vhd" 36 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}