step_a.tan.qmsg

来自「步进的控制电机控制 c++环境下开发」· QMSG 代码 · 共 10 行 · 第 1/5 页

{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off step_a -c step_a --timing_analysis_only " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off step_a -c step_a --timing_analysis_only" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "F1HZ " "Info: Assuming node F1HZ is an undefined clock" {  } { { "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/step_a.bdf" "" "" { Schematic "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/step_a.bdf" { { 816 256 424 832 "F1HZ" "" } } } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "F1HZ" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "D_STP " "Info: Assuming node D_STP is an undefined clock" {  } { { "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/step_a.bdf" "" "" { Schematic "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/step_a.bdf" { { 552 168 336 568 "D_STP" "" } } } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "D_STP" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk0 " "Info: Assuming node clk0 is an undefined clock" {  } { { "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/step_a.bdf" "" "" { Schematic "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/step_a.bdf" { { 320 176 344 336 "clk0" "" } } } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "clk0" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "altera_internal_jtag~TCKUTAP " "Info: Assuming node altera_internal_jtag~TCKUTAP is an undefined clock" {  } { { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TCKUTAP" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk5 " "Info: Assuming node clk5 is an undefined clock" {  } { { "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/step_a.bdf" "" "" { Schematic "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/step_a.bdf" { { 280 184 352 296 "clk5" "" } { 592 80 128 608 "CLK5" "" } } } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "clk5" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "CNTT " "Info: Assuming node CNTT is an undefined clock" {  } { { "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/step_a.bdf" "" "" { Schematic "D:/DesignWorkspace/SOPCWorkspace/step_1C6A/step_a.bdf" { { 840 256 424 856 "CNTT" "" } } } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "CNTT" } } } }  } 0}  } {  } 0}