step_a.hif

来自「步进的控制电机控制 c++环境下开发」· HIF 代码 · 共 4,393 行 · 第 1/5 页

Version 4.1 Build 181 06/29/2004 SJ Full Version
31
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synplcty.lmf
# entity
cmp3
# case_insensitive
# source_file
cmp3.gdf
1098885278
5
# storage
db|step_a.(2).cnf
db|step_a.(2).cnf
# end
# entity
DECD
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
decd.vhd
1106882862
4
# storage
db|step_a.(7).cnf
db|step_a.(7).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
CNT5
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cnt5.vhd
1106882168
4
# storage
db|step_a.(8).cnf
db|step_a.(8).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
FREQTEST
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
freqtest.vhd
1102562350
4
# storage
db|step_a.(9).cnf
db|step_a.(9).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
TESTCTL
# architecture
A:behav
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
testctl.vhd
949386254
4
# storage
db|step_a.(10).cnf
db|step_a.(10).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
REG
# architecture
A:SYN
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
reg.vhd
1102562472
4
# storage
db|step_a.(11).cnf
db|step_a.(11).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
CNT
# architecture
A:SYN
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cnt.vhd
1102562426
4
# storage
db|step_a.(13).cnf
db|step_a.(13).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
cntr_8f8
# case_insensitive
# source_file
db|cntr_8f8.tdf
1106884916
6
# storage
db|step_a.(15).cnf
db|step_a.(15).cnf
# used_port {
clock
clk_en
aclr
q0
q1
q2
q3
q4
q5
q6
q7
q8
q9
q10
q11
q12
q13
q14
q15
cout
}
# end
# entity
mux_6fc
# case_insensitive
# source_file
db|mux_6fc.tdf
1106884916
6
# storage
db|step_a.(18).cnf
db|step_a.(18).cnf
# used_port {
data0
data1
data2
data3
data4
data5
data6
data7
sel0
result0
result1
result2
result3
}
# end
# entity
CNT24
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cnt24.vhd
1106701802
4
# storage
db|step_a.(20).cnf
db|step_a.(20).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
altsyncram_2nm
# case_insensitive
# source_file
db|altsyncram_2nm.tdf
1106884918
6
# storage
db|step_a.(24).cnf
db|step_a.(24).cnf
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
clock0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
q_a8
q_a9
q_a10
q_a11
q_a12
q_a13
q_a14
q_a15
}
# memory_file {
.\pwm_1.mif
1099451084
}
# end
# entity
CNT8
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cnt8.vhd
1106879212
4
# storage
db|step_a.(25).cnf
db|step_a.(25).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
cntr_ds6
# case_insensitive
# source_file
db|cntr_ds6.tdf
1106884920
6
# storage
db|step_a.(27).cnf
db|step_a.(27).cnf
# used_port {
clock
q0
q1
q2
q3
q4
}
# end
# entity
cntr_rq5
# case_insensitive
# source_file
db|cntr_rq5.tdf
1106884920
6
# storage
db|step_a.(29).cnf
db|step_a.(29).cnf
# used_port {
clock
updown
q0
q1
q2
q3
q4
}
# end
# entity
rom3
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
rom3.vhd
1106890282
4
# storage
db|step_a.(30).cnf
db|step_a.(30).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
altsyncram_0fs
# case_insensitive
# source_file
db|altsyncram_0fs.tdf
1106890490
6
# storage
db|step_a.(32).cnf
db|step_a.(32).cnf
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
clock0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
q_a8
q_a9
q_a10
q_a11
q_a12
q_a13
q_a14
q_a15
}
# end
# entity
altsyncram_s6a2
# case_insensitive
# source_file
db|altsyncram_s6a2.tdf
1106890490
6
# storage
db|step_a.(33).cnf
db|step_a.(33).cnf
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_b0
address_b1
address_b2
address_b3
address_b4
clock0
clock1
data_b0
data_b1
data_b2
data_b3
data_b4
data_b5
data_b6
data_b7
data_b8
data_b9
data_b10
data_b11
data_b12
data_b13
data_b14
data_b15
wren_b
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
q_a8
q_a9
q_a10
q_a11
q_a12
q_a13
q_a14
q_a15
q_b0
q_b1
q_b2
q_b3
q_b4
q_b5
q_b6
q_b7
q_b8
q_b9
q_b10
q_b11
q_b12
q_b13
q_b14
q_b15
}
# memory_file {
PWM_1.mif
1099451084
}
# end
# entity
decode_9ie
# case_insensitive
# source_file
db|decode_9ie.tdf
1106890494
6
# storage
db|step_a.(40).cnf
db|step_a.(40).cnf
# used_port {
aclr
clken
clock
data0
data1
data2
enable
eq0
eq1
eq2
eq3
eq4
eq5
eq6
eq7
}
# end
# entity
cntr_s98
# case_insensitive
# source_file
db|cntr_s98.tdf
1106890496
6
# storage
db|step_a.(46).cnf
db|step_a.(46).cnf
# used_port {
data0
data1
data2
data3
data4
clock
aclr
sload
q0
q1
q2
q3
q4
}
# end
# entity
cntr_qd8
# case_insensitive
# source_file
db|cntr_qd8.tdf
1106890496
6
# storage
db|step_a.(48).cnf
db|step_a.(48).cnf
# used_port {
clock
cnt_en
aclr
sclr
q0
q1
q2
q3
q4
}
# end
# entity
21mux
# case_insensitive
# source_file
d:|altera|quartus41|libraries|others|maxplus2|21mux.bdf
1081473736
23
# storage
db|step_a.(1).cnf
db|step_a.(1).cnf
# end
# entity
lpm_compare
# case_insensitive
# source_file
d:|altera|quartus41|libraries|megafunctions|LPM_COMPARE.tdf
1088009428
6
# storage
db|step_a.(3).cnf
db|step_a.(3).cnf
# user_parameter {
lpm_width
4
PARAMETER_UNKNOWN
USR
LPM_REPRESENTATION
UNSIGNED
PARAMETER_UNKNOWN
DEF
LPM_PIPELINE
0
PARAMETER_UNKNOWN
DEF
CHAIN_SIZE
8
PARAMETER_UNKNOWN
DEF
ONE_INPUT_IS_CONSTANT
NO
PARAMETER_UNKNOWN
DEF
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CASCADE_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
CASCADE_CHAIN_LENGTH
2
CASCADE_CHAIN_LENGTH
USR
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
NOTHING
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
agb
dataa0
dataa1
dataa2
dataa3
datab0
datab1
datab2
datab3
}
# include_file {
d:|altera|quartus41|libraries|megafunctions|comptree.inc
1081478110
d:|altera|quartus41|libraries|megafunctions|altshift.inc
1081477602
d:|altera|quartus41|libraries|megafunctions|aglobal41.inc
1088009406
}
# end
# entity
comptree
# case_insensitive
# source_file
d:|altera|quartus41|libraries|megafunctions|comptree.tdf
1088009428
6
# storage
db|step_a.(4).cnf
db|step_a.(4).cnf
# user_parameter {
lpm_width
4
PARAMETER_UNKNOWN
USR
CHAIN_LENGTH
48
PARAMETER_UNKNOWN
USR
ONE_INPUT_CONSTANT
0
PARAMETER_UNKNOWN
USR
OUTPUTS_CLOCKED
0
PARAMETER_UNKNOWN
USR
BURRIED_CLOCKED
1
PARAMETER_UNKNOWN
USR
MODE
0
PARAMETER_UNKNOWN
USR
}
# used_port {
dataa0
dataa1
dataa2
dataa3
datab0
datab1
datab2
datab3
agb
}
# include_file {
d:|altera|quartus41|libraries|megafunctions|comptree.inc
1081478110
d:|altera|quartus41|libraries|megafunctions|cmpchain.inc
1081478062
d:|altera|quartus41|libraries|megafunctions|lpm_constant.inc
1081478554
}
# end
# entity
cmpchain
# case_insensitive
# source_file
d:|altera|quartus41|libraries|megafunctions|cmpchain.tdf
1088009428
6
# storage
db|step_a.(5).cnf
db|step_a.(5).cnf
# user_parameter {
lpm_width
4
PARAMETER_UNKNOWN
USR
ONE_INPUT_CONSTANT
0
PARAMETER_UNKNOWN
USR
MODE
0
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CASCADE_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
CASCADE_CHAIN_LENGTH
2
CASCADE_CHAIN_LENGTH
USR
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
dataa0
dataa1
dataa2
dataa3
datab0
datab1
datab2
datab3
agb
}
# include_file {
d:|altera|quartus41|libraries|megafunctions|comptree.inc
1081478110
d:|altera|quartus41|libraries|megafunctions|aglobal41.inc
1088009406
}
# end
# entity
altshift
# case_insensitive
# source_file
d:|altera|quartus41|libraries|megafunctions|altshift.tdf
1088009432
6
# storage
db|step_a.(6).cnf
db|step_a.(6).cnf
# user_parameter {
WIDTH
1
PARAMETER_UNKNOWN
USR
DEPTH
0
PARAMETER_UNKNOWN
USR
}
# used_port {
data0
result0
}
# end
# entity
lpm_ff
# case_insensitive
# source_file
d:|altera|quartus41|libraries|megafunctions|lpm_ff.tdf
1088009430
6
# storage
db|step_a.(12).cnf
db|step_a.(12).cnf
# user_parameter {
LPM_WIDTH
16
PARAMETER_DEC
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_FFTYPE