step_a.tan.rpt

来自「步进的控制电机控制 c++环境下开发」· RPT 代码 · 共 226 行 · 第 1/5 页

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+----------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                               ;
+-------------------------------------------------------+--------------------+------+----+
; Option                                                ; Setting            ; From ; To ;
+-------------------------------------------------------+--------------------+------+----+
; Device name                                           ; EP1C6Q240C8        ;      ;    ;
; Timing Models                                         ; Production         ;      ;    ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;
; Number of paths to report                             ; 200                ;      ;    ;
; Minimum tpd to report                                 ; 0.0NS              ;      ;    ;
; Run Minimum Analysis                                  ; On                 ;      ;    ;
; Use Minimum Timing Models                             ; Off                ;      ;    ;
; Report IO Paths Separately                            ; Off                ;      ;    ;
; Clock Analysis Only                                   ; Off                ;      ;    ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;
; Cut off read during write signal paths                ; Off                ;      ;    ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;
; fmax Requirement                                      ; 10.0 ns            ;      ;    ;
; Ignore Clock Settings                                 ; On                 ;      ;    ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;
+-------------------------------------------------------+--------------------+------+----+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                              ;
+---------------------------------------------+----------+-----------------------------------+------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Type                                        ; Slack    ; Required Time                     ; Actual Time                                    ; From                                                                                                                                ; To                                                                                                                                  ; From Clock                   ; To Clock                     ; Failed Paths ;
+---------------------------------------------+----------+-----------------------------------+------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Worst-case tsu                              ; N/A      ; None                              ; -0.347 ns                                      ; altera_internal_jtag~TMSUTAP                                                                                                        ; sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0]                                                                                       ;                              ; altera_internal_jtag~TCKUTAP ; 0            ;
; Worst-case tco                              ; N/A      ; None                              ; 25.186 ns                                      ; rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|ram_block3a15~porta_datain_reg9 ; Y[2]                                                                                                                                ; clk0                         ;                              ; 0            ;
; Worst-case tpd                              ; N/A      ; None                              ; 13.730 ns                                      ; S                                                                                                                                   ; Y[2]                                                                                                                                ;                              ;                              ; 0            ;
; Worst-case th                               ; N/A      ; None                              ; 3.795 ns                                       ; altera_internal_jtag                                                                                                                ; sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[9]                                                                          ;                              ; altera_internal_jtag~TCKUTAP ; 0            ;
; Worst-case Minimum tco                      ; N/A      ; None                              ; 14.314 ns                                      ; FREQTEST:121|REG:U2|lpm_ff:lpm_ff_component|dffs[9]                                                                                 ; D[9]                                                                                                                                ; F1HZ                         ;                              ; 0            ;
; Worst-case Minimum tpd                      ; N/A      ; None                              ; 2.124 ns                                       ; altera_internal_jtag~TDO                                                                                                            ; altera_reserved_tdo                                                                                                                 ;                              ;                              ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; 1.863 ns ; 100.00 MHz ( period = 10.000 ns ) ; 159.39 MHz ( period = 6.274 ns )               ; sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1]                                                                                  ; sld_hub:sld_hub_inst|HUB_TDO~reg0                                                                                                   ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'clk0'                         ; 4.924 ns ; 100.00 MHz ( period = 10.000 ns ) ; 197.01 MHz ( period = 5.076 ns )               ; rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|ram_block3a15~porta_datain_reg0 ; rom3:inst|altsyncram:altsyncram_component|altsyncram_0fs:auto_generated|altsyncram_s6a2:altsyncram1|ram_block3a15~porta_memory_reg0 ; clk0                         ; clk0                         ; 0            ;