freqtest.rpt
来自「步进的控制电机控制 c++环境下开发」· RPT 代码 · 共 805 行 · 第 1/3 页
RPT
805 行
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\xd_dsp\disk7\step_new2\freqtest.rpt
freqtest
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - B 10 DFFE + 0 2 0 4 |CNT:U3|lpm_counter:lpm_counter_component|dffs0
- 7 - B 10 DFFE + 0 3 0 3 |CNT:U3|lpm_counter:lpm_counter_component|dffs1
- 2 - B 02 DFFE + 0 4 0 2 |CNT:U3|lpm_counter:lpm_counter_component|dffs2
- 7 - B 02 DFFE + 0 3 0 3 |CNT:U3|lpm_counter:lpm_counter_component|dffs3
- 8 - B 02 DFFE + 0 4 0 2 |CNT:U3|lpm_counter:lpm_counter_component|dffs4
- 2 - B 07 DFFE + 0 3 0 4 |CNT:U3|lpm_counter:lpm_counter_component|dffs5
- 4 - B 07 DFFE + 0 4 0 3 |CNT:U3|lpm_counter:lpm_counter_component|dffs6
- 7 - B 07 DFFE + 0 4 0 2 |CNT:U3|lpm_counter:lpm_counter_component|dffs7
- 3 - B 09 DFFE + 0 3 0 4 |CNT:U3|lpm_counter:lpm_counter_component|dffs8
- 4 - B 09 DFFE + 0 4 0 3 |CNT:U3|lpm_counter:lpm_counter_component|dffs9
- 8 - B 09 DFFE + 0 4 0 2 |CNT:U3|lpm_counter:lpm_counter_component|dffs10
- 1 - B 12 DFFE + 0 3 0 4 |CNT:U3|lpm_counter:lpm_counter_component|dffs11
- 4 - B 12 DFFE + 0 4 0 3 |CNT:U3|lpm_counter:lpm_counter_component|dffs12
- 8 - B 12 DFFE + 0 4 0 2 |CNT:U3|lpm_counter:lpm_counter_component|dffs13
- 1 - B 10 DFFE + 0 3 0 3 |CNT:U3|lpm_counter:lpm_counter_component|dffs14
- 2 - B 10 DFFE + 0 4 0 2 |CNT:U3|lpm_counter:lpm_counter_component|dffs15
- 3 - B 02 AND2 0 3 0 3 |CNT:U3|lpm_counter:lpm_counter_component|lpm_add_sub:add_sub|addcore:adder|:107
- 4 - B 02 AND2 0 3 0 4 |CNT:U3|lpm_counter:lpm_counter_component|lpm_add_sub:add_sub|addcore:adder|:115
- 5 - B 07 AND2 0 2 0 1 |CNT:U3|lpm_counter:lpm_counter_component|lpm_add_sub:add_sub|addcore:adder|:119
- 1 - B 07 AND2 0 4 0 4 |CNT:U3|lpm_counter:lpm_counter_component|lpm_add_sub:add_sub|addcore:adder|:127
- 7 - B 09 AND2 0 2 0 1 |CNT:U3|lpm_counter:lpm_counter_component|lpm_add_sub:add_sub|addcore:adder|:131
- 6 - B 09 AND2 0 4 0 4 |CNT:U3|lpm_counter:lpm_counter_component|lpm_add_sub:add_sub|addcore:adder|:139
- 7 - B 12 AND2 0 2 0 1 |CNT:U3|lpm_counter:lpm_counter_component|lpm_add_sub:add_sub|addcore:adder|:143
- 5 - B 12 AND2 0 4 0 3 |CNT:U3|lpm_counter:lpm_counter_component|lpm_add_sub:add_sub|addcore:adder|:151
- 8 - B 10 AND2 0 3 1 0 |CNT:U3|lpm_counter:lpm_counter_component|lpm_add_sub:add_sub|addcore:adder|:159
- 5 - B 10 DFFE 0 2 1 0 |REG:U2|lpm_ff:lpm_ff_component|dffs0
- 3 - B 03 DFFE 0 2 1 0 |REG:U2|lpm_ff:lpm_ff_component|dffs1
- 1 - B 02 DFFE 0 2 1 0 |REG:U2|lpm_ff:lpm_ff_component|dffs2
- 6 - B 02 DFFE 0 2 1 0 |REG:U2|lpm_ff:lpm_ff_component|dffs3
- 5 - B 02 DFFE 0 2 1 0 |REG:U2|lpm_ff:lpm_ff_component|dffs4
- 3 - B 07 DFFE 0 2 1 0 |REG:U2|lpm_ff:lpm_ff_component|dffs5
- 8 - B 07 DFFE 0 2 1 0 |REG:U2|lpm_ff:lpm_ff_component|dffs6
- 6 - B 07 DFFE 0 2 1 0 |REG:U2|lpm_ff:lpm_ff_component|dffs7
- 2 - B 09 DFFE 0 2 1 0 |REG:U2|lpm_ff:lpm_ff_component|dffs8
- 1 - B 09 DFFE 0 2 1 0 |REG:U2|lpm_ff:lpm_ff_component|dffs9
- 5 - B 09 DFFE 0 2 1 0 |REG:U2|lpm_ff:lpm_ff_component|dffs10
- 2 - B 12 DFFE 0 2 1 0 |REG:U2|lpm_ff:lpm_ff_component|dffs11
- 3 - B 12 DFFE 0 2 1 0 |REG:U2|lpm_ff:lpm_ff_component|dffs12
- 6 - B 12 DFFE 0 2 1 0 |REG:U2|lpm_ff:lpm_ff_component|dffs13
- 6 - B 10 DFFE 0 2 1 0 |REG:U2|lpm_ff:lpm_ff_component|dffs14
- 4 - B 10 DFFE 0 2 1 0 |REG:U2|lpm_ff:lpm_ff_component|dffs15
- 2 - B 03 DFFE + 0 0 0 33 |TESTCTL:U1|Div2CLK (|TESTCTL:U1|:5)
- 1 - B 03 OR2 ! 1 1 0 16 |TESTCTL:U1|:36
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: f:\xd_dsp\disk7\step_new2\freqtest.rpt
freqtest
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 11/ 96( 11%) 6/ 48( 12%) 0/ 48( 0%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
09: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\xd_dsp\disk7\step_new2\freqtest.rpt
freqtest
** CLOCK SIGNALS **
Type Fan-out Name
DFF 34 |TESTCTL:U1|Div2CLK
INPUT 16 FSIN
INPUT 2 CLK
Device-Specific Information: f:\xd_dsp\disk7\step_new2\freqtest.rpt
freqtest
** CLEAR SIGNALS **
Type Fan-out Name
LCELL 16 |TESTCTL:U1|:36
Device-Specific Information: f:\xd_dsp\disk7\step_new2\freqtest.rpt
freqtest
** EQUATIONS **
CLK : INPUT;
FSIN : INPUT;
-- Node name is 'CCOUT'
-- Equation name is 'CCOUT', type is output
CCOUT = _LC8_B10;
-- Node name is 'DOUT0'
-- Equation name is 'DOUT0', type is output
DOUT0 = _LC5_B10;
-- Node name is 'DOUT1'
-- Equation name is 'DOUT1', type is output
DOUT1 = _LC3_B3;
-- Node name is 'DOUT2'
-- Equation name is 'DOUT2', type is output
DOUT2 = _LC1_B2;
-- Node name is 'DOUT3'
-- Equation name is 'DOUT3', type is output
DOUT3 = _LC6_B2;
-- Node name is 'DOUT4'
-- Equation name is 'DOUT4', type is output
DOUT4 = _LC5_B2;
-- Node name is 'DOUT5'
-- Equation name is 'DOUT5', type is output
DOUT5 = _LC3_B7;
-- Node name is 'DOUT6'
-- Equation name is 'DOUT6', type is output
DOUT6 = _LC8_B7;
-- Node name is 'DOUT7'
-- Equation name is 'DOUT7', type is output
DOUT7 = _LC6_B7;
-- Node name is 'DOUT8'
-- Equation name is 'DOUT8', type is output
DOUT8 = _LC2_B9;
-- Node name is 'DOUT9'
-- Equation name is 'DOUT9', type is output
DOUT9 = _LC1_B9;
-- Node name is 'DOUT10'
-- Equation name is 'DOUT10', type is output
DOUT10 = _LC5_B9;
-- Node name is 'DOUT11'
-- Equation name is 'DOUT11', type is output
DOUT11 = _LC2_B12;
-- Node name is 'DOUT12'
-- Equation name is 'DOUT12', type is output
DOUT12 = _LC3_B12;
-- Node name is 'DOUT13'
-- Equation name is 'DOUT13', type is output
DOUT13 = _LC6_B12;
-- Node name is 'DOUT14'
-- Equation name is 'DOUT14', type is output
DOUT14 = _LC6_B10;
-- Node name is 'DOUT15'
-- Equation name is 'DOUT15', type is output
DOUT15 = _LC4_B10;
-- Node name is '|CNT:U3|lpm_counter:lpm_counter_component|dffs0' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is '_LC3_B10', type is buried
_LC3_B10 = DFFE(!_LC3_B10, GLOBAL( FSIN), !_LC1_B3, VCC, _LC2_B3);
-- Node name is '|CNT:U3|lpm_counter:lpm_counter_component|dffs1' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is '_LC7_B10', type is buried
_LC7_B10 = DFFE( _EQ001, GLOBAL( FSIN), !_LC1_B3, VCC, _LC2_B3);
_EQ001 = !_LC3_B10 & _LC7_B10
# _LC3_B10 & !_LC7_B10;
-- Node name is '|CNT:U3|lpm_counter:lpm_counter_component|dffs2' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is '_LC2_B2', type is buried
_LC2_B2 = DFFE( _EQ002, GLOBAL( FSIN), !_LC1_B3, VCC, _LC2_B3);
_EQ002 = _LC2_B2 & !_LC7_B10
# _LC2_B2 & !_LC3_B10
# !_LC2_B2 & _LC3_B10 & _LC7_B10;
-- Node name is '|CNT:U3|lpm_counter:lpm_counter_component|dffs3' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is '_LC7_B2', type is buried
_LC7_B2 = DFFE( _EQ003, GLOBAL( FSIN), !_LC1_B3, VCC, _LC2_B3);
_EQ003 = !_LC3_B2 & _LC7_B2
# _LC3_B2 & !_LC7_B2;
-- Node name is '|CNT:U3|lpm_counter:lpm_counter_component|dffs4' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is '_LC8_B2', type is buried
_LC8_B2 = DFFE( _EQ004, GLOBAL( FSIN), !_LC1_B3, VCC, _LC2_B3);
_EQ004 = !_LC7_B2 & _LC8_B2
# !_LC3_B2 & _LC8_B2
# _LC3_B2 & _LC7_B2 & !_LC8_B2;
-- Node name is '|CNT:U3|lpm_counter:lpm_counter_component|dffs5' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is '_LC2_B7', type is buried
_LC2_B7 = DFFE( _EQ005, GLOBAL( FSIN), !_LC1_B3, VCC, _LC2_B3);
_EQ005 = _LC2_B7 & !_LC4_B2
# !_LC2_B7 & _LC4_B2;
-- Node name is '|CNT:U3|lpm_counter:lpm_counter_component|dffs6' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is '_LC4_B7', type is buried
_LC4_B7 = DFFE( _EQ006, GLOBAL( FSIN), !_LC1_B3, VCC, _LC2_B3);
_EQ006 = !_LC2_B7 & _LC4_B7
# !_LC4_B2 & _LC4_B7
# _LC2_B7 & _LC4_B2 & !_LC4_B7;
-- Node name is '|CNT:U3|lpm_counter:lpm_counter_component|dffs7' from file "lpm_counter.tdf" line 234, column 10
-- Equation name is '_LC7_B7', type is buried
_LC7_B7 = DFFE( _EQ007, GLOBAL( FSIN), !_LC1_B3, VCC, _LC2_B3);
_EQ007 = !_LC5_B7 & _LC7_B7
# !_LC4_B7 & _LC7_B7
# _LC4_B7 & _LC5_B7 & !_LC7_B7;
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