run

这是一个I2C接口的VHDL实现

#!/bin/csh

set i2c      = ../../../..
set bench    = $i2c/bench
set wave_dir = $i2c/sim/rtl_sim/i2c_verilog/waves

ncverilog							\
								\
	+access+rwc +linedebug					\
	+define+WAVES						\
								\
	+incdir+$bench/verilog					\
	+incdir+$i2c/rtl/verilog				\
								\
	+libext+.v						\
	-y $SYNOPSYS/dw/sim_ver/				\
								\
								\
	$i2c/rtl/verilog/i2c_master_bit_ctrl.v			\
	$i2c/rtl/verilog/i2c_master_byte_ctrl.v			\
	$i2c/rtl/verilog/i2c_master_top.v			\
								\
	$bench/verilog/i2c_slave_model.v			\
	$bench/verilog/wb_master_model.v			\
	$bench/verilog/tst_bench_top.v