clock_pack.vhd

来自「設計VHDL24小時的時鐘」· VHDL 代码 · 共 58 行

--*************************************
--*  Declare All Component Which Is   *
--*  Used In SEVEN_SCAN_CLOCK_24.VHD  *
--*     Filename : CLOCK_PACK.VHD     *
--*************************************

library IEEE;
use IEEE.STD_LOGIC_1164.all;

package CLOCK_PACK is

component CLK_SET
  port( CLK       : in std_logic;
	   RESET     : in std_logic;
        SCAN_CLK  : out std_logic;
	   COUNT_CLK : out std_logic);
end component;

component COUNT_0_9
  Port ( CLK   : in std_logic;
         RESET : in std_logic;
	    CE    : in std_logic;
	    CARRY : out std_logic;
	    BCD   : out std_logic_vector(3 downto 0));  
end component;

component COUNT_0_5
  Port ( CLK   : in std_logic;
         RESET : in std_logic;
	    CE    : in std_logic;
	    CARRY : out std_logic;
	    BCD   : out std_logic_vector(3 downto 0));  
end component;

component COUNT_00_59
  Port ( CLK   : in std_logic;
         RESET : in std_logic;
	    CE    : in std_logic;
	    CARRY : out std_logic;
	    BCD   : out std_logic_vector(7 downto 0));
end component;

component COUNT_00_23
  Port ( CLK      : in std_logic;
         RESET    : in std_logic;
	    CE       : in std_logic;
	    HOUR_BCD : out std_logic_vector(7 downto 0));
end component;


component DECODER
  port ( CLK     : in std_logic;
         BCD     : in std_logic_vector(3 downto 0);
 	    SEGMENT : out std_logic_vector(7 downto 0));
end component;

end CLOCK_PACK;