segment_scan_clock_24.npl

来自「設計VHDL24小時的時鐘」· NPL 代码 · 共 41 行

JDF G
// Converted from an earlier version by Project Navigator version 5
PROJECT SEGMENT_SCAN_CLOCK_24
DESIGN segment_scan_clock_24 Normal
DEVFAM spartan2
DEVFAMTIME 0
DEVICE xc2s200
DEVICETIME 0
DEVPKG pq208
DEVPKGTIME 0
DEVSPEED -5
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Modelsim
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
MODULE COUNT_0_9.VHD
MODSTYLE count_0_9 Normal
MODULE SEGMENT_SCAN_CLOCK_24.VHD
MODSTYLE segment_scan_clock_24 Normal
MODULE COUNT_00_59.VHD
MODSTYLE count_00_59 Normal
MODULE DECODER.vhd
MODSTYLE decoder Normal
MODULE COUNT_0_5.VHD
MODSTYLE count_0_5 Normal
MODULE CLK_SET.VHD
MODSTYLE clk_set Normal
MODULE COUNT_00_23.VHD
MODSTYLE count_00_23 Normal
LIBFILE CLOCK_PACK.vhd work ***
DEPASSOC segment_scan_clock_24 SEGMENT_SCAN_CLOCK_24CF.ucf Normal
[STATUS-ALL]
segment_scan_clock_24.ngcFile=WARNINGS,1073229106
[STRATEGY-LIST]
Normal=True