segment_scan_clock_24.twr

来自「設計VHDL24小時的時鐘」· TWR 代码 · 共 63 行

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Release 6.1i Trace G.23
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.

C:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml segment_scan_clock_24
segment_scan_clock_24.ncd -o segment_scan_clock_24.twr
segment_scan_clock_24.pcf


Design file:              segment_scan_clock_24.ncd
Physical constraint file: segment_scan_clock_24.pcf
Device,speed:             xc2s200,-5 (PRODUCTION 1.27 2003-06-19)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.

================================================================================
Timing constraint: TS_CLK = PERIOD TIMEGRP "CLK"  25 nS   HIGH 50.000000 % ;

 325 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum period is   6.010ns.
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All constraints were met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock to Setup on destination clock CLK
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLK            |    6.010|         |         |         |
---------------+---------+---------+---------+---------+


Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover 325 paths, 0 nets, and 51 connections

Design statistics:
   Minimum period:   6.010ns (Maximum frequency: 166.389MHz)


Analysis completed Sun Jan 04 23:12:25 2004
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Peak Memory Usage: 49 MB