count_0_9.vhd

来自「設計VHDL24小時的時鐘」· VHDL 代码 · 共 43 行

--********************************
--*     Counter From 0 To 9      *
--*   Filename : COUNT_0_9.VHD   *
--********************************

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity COUNT_0_9 is
    Port ( CLK   : in std_logic;
           RESET : in std_logic;
		 CE    : in std_logic;
		 CARRY : out std_logic;
		 BCD   : out std_logic_vector(3 downto 0));
end COUNT_0_9;

architecture Behavioral of COUNT_0_9 is
  signal NINE    : std_logic;
  signal COUNTER : std_logic_vector(3 downto 0);
begin
  process (CLK,RESET)

    begin
      if RESET    = '0' then 
	    COUNTER <= "0000";
 	 elsif CLK'event and CLK = '1' then
	   if CE     = '1' then
	      if COUNTER  = "1001" then
	         COUNTER <= "0000";
	 	 else
	         COUNTER <= COUNTER + 1;
		 end if;
	   end if;
	 end if;
  end process;
  NINE  <= '1' when COUNTER = "1001" else '0'; 
  CARRY <= NINE and CE;
  BCD   <= COUNTER; 
    
end Behavioral;