segment_scan_clock_24.par

設計VHDL24小時的時鐘

Constraints file: segment_scan_clock_24.pcf

Loading device database for application Par from file
"segment_scan_clock_24_map.ncd".
   "segment_scan_clock_24" is an NCD, version 2.38, device xc2s200, package
pq208, speed -5
Loading device for application Par from file 'v200.nph' in environment
C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-06-19.


Resolved that IOB <SEGMENT<0>> must be placed at site P34.
Resolved that IOB <SEGMENT<1>> must be placed at site P23.
Resolved that IOB <SEGMENT<2>> must be placed at site P24.
Resolved that IOB <SEGMENT<3>> must be placed at site P27.
Resolved that IOB <ENABLE<1>> must be placed at site P43.
Resolved that IOB <SEGMENT<4>> must be placed at site P29.
Resolved that IOB <ENABLE<2>> must be placed at site P42.
Resolved that IOB <SEGMENT<5>> must be placed at site P30.
Resolved that IOB <ENABLE<3>> must be placed at site P41.
Resolved that IOB <SEGMENT<6>> must be placed at site P31.
Resolved that IOB <SEGMENT<7>> must be placed at site P33.
Resolved that IOB <ENABLE<4>> must be placed at site P37.
Resolved that IOB <ENABLE<5>> must be placed at site P36.
Resolved that IOB <ENABLE<6>> must be placed at site P35.
Resolved that GCLKIOB <CLK> must be placed at site P80.
Resolved that IOB <RESET> must be placed at site P180.


Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            15 out of 140    10%
      Number of LOCed External IOBs   15 out of 15    100%

   Number of SLICEs                   60 out of 2352    2%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

Starting initial Timing Analysis.  REAL time: 0 secs 
Finished initial Timing Analysis.  REAL time: 0 secs 


Phase 1.1
Phase 1.1 (Checksum:989800) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
..
.
Phase 5.8 (Checksum:999aa7) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file segment_scan_clock_24.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 404 unrouted;       REAL time: 0 secs 

Phase 2: 360 unrouted;       REAL time: 24 secs 

Phase 3: 83 unrouted;       REAL time: 24 secs 

Phase 4: 83 unrouted; (0)      REAL time: 24 secs 

Phase 5: 83 unrouted; (0)      REAL time: 24 secs 

Phase 6: 83 unrouted; (0)      REAL time: 24 secs 

Phase 7: 0 unrouted; (0)      REAL time: 24 secs 

Total REAL time to Router completion: 25 secs 
Total CPU time to Router completion: 24 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         CLK_BUFGP          |  Global  |   13   |  0.000     |  0.759      |
+----------------------------+----------+--------+------------+-------------+
|   TIME_BASE_DIVIDER<25>    |   Local  |   19   |  1.995     |  3.964      |
+----------------------------+----------+--------+------------+-------------+
|   TIME_BASE_DIVIDER<15>    |   Local  |    5   |  0.104     |  3.424      |
+----------------------------+----------+--------+------------+-------------+
|            _n0030          |   Local  |    4   |  0.041     |  3.283      |
+----------------------------+----------+--------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 218


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        1.586
   The MAXIMUM PIN DELAY IS:                               6.402
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   2.990

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 7.00  d >= 7.00
   ---------   ---------   ---------   ---------   ---------   ---------
         139         201          13          21          30           0

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  TS_CLK = PERIOD TIMEGRP "CLK"  25 nS   HI | 25.000ns   | 6.010ns    | 13   
  GH 50.000000 %                            |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 25 secs 
Total CPU time to PAR completion: 25 secs 

Peak Memory Usage:  69 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Writing design to file segment_scan_clock_24.ncd.


PAR done.