count_00_59.vhd

来自「設計VHDL24小時的時鐘」· VHDL 代码 · 共 27 行

--*********************************
--*  2 Dig Counter From 00 To 59  *
--*  Filename : COUNT_00_59.VHD   *
--*********************************

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.CLOCK_PACK.all;
 
entity COUNT_00_59 is
    Port ( CLK   : in std_logic;
           RESET : in std_logic;
           CE    : in std_logic;
           CARRY : out std_logic;
 		 BCD   : out std_logic_vector(7 downto 0)); 
end COUNT_00_59;

architecture Behavioral of COUNT_00_59 is
  signal CARRY10 : std_logic; 
begin
  
COUNTER   : COUNT_0_9 port map (CLK,RESET,CE     ,CARRY10,BCD(3 downto 0));
COUNTER10 : COUNT_0_5 port map (CLK,RESET,CARRY10,CARRY  ,BCD(7 downto 4));
end Behavioral;