clk_set.vhd

来自「設計VHDL24小時的時鐘」· VHDL 代码 · 共 34 行

--**********************************
--*      Time Base Generator       *
--*     Filename : CLK_SET.VHD     *
--**********************************

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity CLK_SET is
    Port ( CLK       : in std_logic;
		 RESET     : in std_logic;
           SCAN_CLK  : out std_logic;
		 COUNT_CLK : out std_logic);
end CLK_SET;

architecture Behavioral of CLK_SET is
  signal DIVIDER : std_logic_vector(25 downto 1);
begin
  process (CLK,RESET)

    begin
      if RESET    = '0' then 
	    DIVIDER <= "0000000000000000000000000";
	 elsif CLK'event and CLK = '1' then
	    DIVIDER <= DIVIDER + 1;
	 end if;
  end process;
  SCAN_CLK  <= DIVIDER(15);
  COUNT_CLK <= DIVIDER(25);

end Behavioral;