segment_scan_clock_24.pcf

設計VHDL24小時的時鐘

SCHEMATIC START ;
// created by map version G.23 on Sun Jan 04 23:11:56 2004 
COMP "SEGMENT<0>" LOCATE =  SITE "P34" LEVEL 1; 
COMP "SEGMENT<1>" LOCATE =  SITE "P23" LEVEL 1; 
COMP "SEGMENT<2>" LOCATE =  SITE "P24" LEVEL 1; 
COMP "SEGMENT<3>" LOCATE =  SITE "P27" LEVEL 1; 
COMP "ENABLE<1>" LOCATE =  SITE "P43" LEVEL 1; 
COMP "SEGMENT<4>" LOCATE =  SITE "P29" LEVEL 1; 
COMP "ENABLE<2>" LOCATE =  SITE "P42" LEVEL 1; 
COMP "SEGMENT<5>" LOCATE =  SITE "P30" LEVEL 1; 
COMP "ENABLE<3>" LOCATE =  SITE "P41" LEVEL 1; 
COMP "SEGMENT<6>" LOCATE =  SITE "P31" LEVEL 1; 
COMP "SEGMENT<7>" LOCATE =  SITE "P33" LEVEL 1; 
COMP "ENABLE<4>" LOCATE =  SITE "P37" LEVEL 1; 
COMP "ENABLE<5>" LOCATE =  SITE "P36" LEVEL 1; 
COMP "ENABLE<6>" LOCATE =  SITE "P35" LEVEL 1; 
COMP "CLK" LOCATE =  SITE "P80" LEVEL 1; 
COMP "RESET" LOCATE =  SITE "P180" LEVEL 1; 
TIMEGRP "CLK" = BEL "TIME_BASE_DIVIDER_23" BEL "TIME_BASE_DIVIDER_24" BEL 
"TIME_BASE_DIVIDER_25" BEL "TIME_BASE_DIVIDER_1" BEL "TIME_BASE_DIVIDER_2" BEL 
"TIME_BASE_DIVIDER_3" BEL "TIME_BASE_DIVIDER_4" BEL "TIME_BASE_DIVIDER_5" BEL 
"TIME_BASE_DIVIDER_6" BEL "TIME_BASE_DIVIDER_7" BEL "TIME_BASE_DIVIDER_8" BEL 
"TIME_BASE_DIVIDER_9" BEL "TIME_BASE_DIVIDER_10" BEL "TIME_BASE_DIVIDER_11" BEL 
"TIME_BASE_DIVIDER_12" BEL "TIME_BASE_DIVIDER_13" BEL "TIME_BASE_DIVIDER_14" 
BEL "TIME_BASE_DIVIDER_15" BEL "TIME_BASE_DIVIDER_16" BEL "TIME_BASE_DIVIDER_17"
 BEL "TIME_BASE_DIVIDER_18" BEL "TIME_BASE_DIVIDER_19" BEL 
"TIME_BASE_DIVIDER_20" BEL "TIME_BASE_DIVIDER_21" BEL "TIME_BASE_DIVIDER_22" ;
TS_CLK = PERIOD TIMEGRP "CLK"  25 nS   HIGH 50.000000 % ;
SCHEMATIC END ;