count_00_23.vhd

設計VHDL24小時的時鐘

--*********************************
--*  2 Dig Counter From 00 To 23  *
--*  Filename : COUNT_00_23.VHD   *
--*********************************

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity COUNT_00_23 is
    Port ( CLK      : in std_logic;
           RESET    : in std_logic;
           CE       : in std_logic;
		 HOUR_BCD : out std_logic_vector(7 downto 0));
end COUNT_00_23;

architecture Behavioral of COUNT_00_23 is
  signal TIME_24  : std_logic;
  signal CLEAR    : std_logic;
  signal TIME_BCD : std_logic_vector(7 downto 0);
begin
  process (CLK,CLEAR)

    begin
      if CLEAR     = '0' then
	    TIME_BCD <= "00000000";
	 elsif CLK'event and CLK = '1' then
	    if CE     = '1' then
	       if TIME_BCD(3 downto 0)  = "1001" then 
	          TIME_BCD(3 downto 0) <= "0000";
			TIME_BCD(7 downto 4) <= TIME_BCD(7 downto 4) + 1;
	       else
	       	TIME_BCD(3 downto 0) <= TIME_BCD(3 downto 0) + 1;
		  end if;
	    end if;
	 end if;
  end process;
  CLEAR    <= RESET and TIME_24;
  TIME_24  <= '0' when TIME_BCD(7 downto 0) = "00100100" else '1';
  HOUR_BCD <= TIME_BCD;

end Behavioral;